To overcome the bandwidth limitation of a random access memory (RAM), a shift register (20) is disposed within the memory array (1) such that the shift register lies parallel to the row lines and is connected to at least one of the bit lines contained within the array. Separate high-speed serial input and output lines (21, 22) are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.