A memory system includes at least a pair of independently addressable dynamic memory module units, each of which includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers coupled to the set of address lines of each memory unit. In response to a memory request, these registers store row and column address portions of a chip address, which are fed in succession to the chips. A multibit adder circuit increments by 1 the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition, thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits detect the condition and cause the timing circuits to generate only the timing signals necessary for accessing the first word location.