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    Distributed priority logic network
    4.
    发明公开
    Distributed priority logic network 失效
    VerteiltesPrioritätslogiknetzwerk。

    公开(公告)号：EP0114523A2

    公开(公告)日：1984-08-01

    申请号：EP83307916.3

    申请日：1983-12-22

    申请人： Honeywell Bull Inc.

    发明人： Boudreau, Daniel A. ,  Salas, Edward R. ,  Sandini, James M.

    IPC分类号： G06F13/36

    CPC分类号： G06F13/37 ,  G06F13/378

    摘要： A bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed, thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively; only one such unit is capable of having the grant of a bus cycle at any given time, whereas any number of such units may have their requests pending at any particular time. The present invention provides a modification to the priority logic which allows a lowest priority unit to be physically positioned at other than the last unit position on the common bus.

    摘要翻译： 一种用于在数据处理系统中耦合多个单元以在其间传送信息的总线。 这些单元以分配的优先级布置耦合，从而在每个单元中提供优先级逻辑，并允许以异步方式生成总线传送周期。 优先级通常基于总线上的物理位置授予，最高优先级给予总线上的第一单元，最低优先级被赋予公车上的最后一个单元。 每个单元包括优先级逻辑，其包括用于请求总线周期的逻辑元件，如果没有其它较高优先级单元也请求了总线周期，则该请求被授权。 在每个单元中存储请求和批准总线周期的指示，分别请求并被授予总线周期; 只有一个这样的单位能够在任何给定时间授予公交车周期，而任何数量的这种单位可以在任何特定的时间等待其请求。 本发明提供了优先级逻辑的修改，其允许最低优先级单元物理地定位在公共总线上的最后单元位置之外。

    Reconfigureable memory system
    5.
    发明公开
    Reconfigureable memory system 失效
    可重构存储系统。

    公开(公告)号：EP0076629A2

    公开(公告)日：1983-04-13

    申请号：EP82305140.4

    申请日：1982-09-29

    申请人： Honeywell Bull Inc.

    发明人： Johnson, Robert B. ,  Salas, Edward R. ,  Nibby, Chester M., Jr.

    IPC分类号： G06F11/20 ,  G06F12/06

    CPC分类号： G11C29/76 ,  G06F11/006 ,  G06F12/0661

    摘要： A memory system comprises a plurality of controllers each of which controls two pairs of daughter boards, each daughter board containing a quarter of the total memory of the controller. Each controller has a set of manually settable switches defining its identity (top end of memory address). Each controller includes reconfiguration apparatus which can be set, by reconfiguration commands, to store a new identity number and use that instead of the manually set number. Further reconfiguration command bits can control the effective arrangement of the daughter boards, dependent on whether the controller is half or fully populated, to put faulty ones off-line. Thus on a memory fault, the complete memory space may be maintained by reconfiguring the controllers within the memory space required.

    Memory system
    6.
    发明公开
    Memory system 失效
    内存系统

    公开(公告)号：EP0076155A2

    公开(公告)日：1983-04-06

    申请号：EP82305139.6

    申请日：1982-09-29

    申请人： Honeywell Bull Inc.

    发明人： Salas, Edward R. ,  Nibby, Chester M., Jr. ,  Johnson, Robert B.

    IPC分类号： G11C8/00 ,  G11C11/24 ,  G06F13/00

    CPC分类号： G06F12/04 ,  G11C8/04 ,  G11C11/4063

    摘要： A memory system includes at least a pair of independently addressable dynamic memory module units, each of which includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers coupled to the set of address lines of each memory unit. In response to a memory request, these registers store row and column address portions of a chip address, which are fed in succession to the chips. A multibit adder circuit increments by 1 the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition, thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits detect the condition and cause the timing circuits to generate only the timing signals necessary for accessing the first word location.

    摘要翻译： 一种存储器系统包括至少一对可独立寻址的动态存储器模块单元，每个动态存储器模块单元包括若干行随机存取存储器（RAM）芯片。 该子系统还包括加法器电路，一对三态操作的地址寄存器电路和定时电路。 地址电路包括耦合到每个存储器单元的一组地址线的一对三态操作地址寄存器。 响应于存储器请求，这些寄存器存储芯片地址的行地址部分和列地址部分，这些地址部分被连续地馈送到芯片。 当存储器请求的最低有效地址位指示子边界地址条件时，多位加法器电路将低位列地址部分递增1，由此使得能够访问一对顺序字位置。 无论何时存储器请求指定不能访问双字的地址，边界电路都检测该条件并使定时电路仅生成访问第一字位置所需的定时信号。