发明公开
- 专利标题: PLL control circuit
- 专利标题(中): PLL控制电路。
-
申请号: EP82109205.3申请日: 1982-10-05
-
公开(公告)号: EP0096106A1公开(公告)日: 1983-12-21
- 发明人: Nishikawa, Meisei , Nakamura, Yukio , Kojima, Tadashi
- 申请人: KABUSHIKI KAISHA TOSHIBA
- 申请人地址: 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址: 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 代理机构: Blumbach Weser Bergen Kramer Zwirner Hoffmann Patentanwälte
- 优先权: JP102818/82 19820615
- 主分类号: G11B5/09
- IPC分类号: G11B5/09 ; H03L7/08
摘要:
A phase locked loop (PLL) control circuit for a digital audio disk system is disclosed which has a voltage-controlled oscillator (VCO) (116), a reference signal generator (106) for generating a reference signal corresponding to the phase state of a digital audio signal when the digital audio signal is reproduced or read out and which is recorded on a digital audio disk (DAD) (54) to have a maximum or minimum inverting period value predetermined by the eight to fourteen modulation (EFM) method, a phase comparator (110) connected to the output terminal of the reference signal generator (106) and the VCO (116), a detector (122) for detecting the maximum inverting period value included in the digital audio signal; and an adder (112) for adding outputs from the phase comparator (110) and the detector (122) and for supplying a sum result as an oscillation control signal to the VCO (116).
公开/授权文献
- EP0096106B1 PLL control circuit 公开/授权日:1986-03-19
信息查询
IPC分类: