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公开(公告)号：EP0098349A3
公开(公告)日：1986-12-10
申请号：EP83102996
申请日：1983-03-25
CPC分类号： G11B27/34 , G11B7/005 , G11B19/28 , G11B20/10527 , G11B20/1423 , G11B20/1806 , G11B27/10 , G11B2220/20
摘要： A circuit is disclosed which is applied for a ditial audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal (102) optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eighteen to fourteen modulation (EFM). The detection circuit includes an edge detector (104) for detecting pulse edges of the digital audio signal (102), a counter (106) for counting pulse edge intervals on the basis of a modulating clock signal (108), a counter type register (114), and a comparator (112). When the register contents of the counter type register (114) is smaller than the count value of the counter (106), the comparator (112) produces a pulse signal (118) by which said register (114) updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal (102) is obtained in a fixed period of time.
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公开(公告)号：EP0098349B1
公开(公告)日：1989-11-15
申请号：EP83102996.2
申请日：1983-03-25
CPC分类号： G11B27/34 , G11B7/005 , G11B19/28 , G11B20/10527 , G11B20/1423 , G11B20/1806 , G11B27/10 , G11B2220/20
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3.发明公开
公开(公告)号：EP0098349A2
公开(公告)日：1984-01-18
申请号：EP83102996.2
申请日：1983-03-25
CPC分类号： G11B27/34 , G11B7/005 , G11B19/28 , G11B20/10527 , G11B20/1423 , G11B20/1806 , G11B27/10 , G11B2220/20
摘要： A circuit is disclosed which is applied for a ditial audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal (102) optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eighteen to fourteen modulation (EFM). The detection circuit includes an edge detector (104) for detecting pulse edges of the digital audio signal (102), a counter (106) for counting pulse edge intervals on the basis of a modulating clock signal (108), a counter type register (114), and a comparator (112). When the register contents of the counter type register (114) is smaller than the count value of the counter (106), the comparator (112) produces a pulse signal (118) by which said register (114) updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal (102) is obtained in a fixed period of time.
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公开(公告)号：EP0096106B1
公开(公告)日：1986-03-19
申请号：EP82109205.3
申请日：1982-10-05
CPC分类号： G11B20/1403 , G11B20/10527
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公开(公告)号：EP0096106A1
公开(公告)日：1983-12-21
申请号：EP82109205.3
申请日：1982-10-05
CPC分类号： G11B20/1403 , G11B20/10527
摘要： A phase locked loop (PLL) control circuit for a digital audio disk system is disclosed which has a voltage-controlled oscillator (VCO) (116), a reference signal generator (106) for generating a reference signal corresponding to the phase state of a digital audio signal when the digital audio signal is reproduced or read out and which is recorded on a digital audio disk (DAD) (54) to have a maximum or minimum inverting period value predetermined by the eight to fourteen modulation (EFM) method, a phase comparator (110) connected to the output terminal of the reference signal generator (106) and the VCO (116), a detector (122) for detecting the maximum inverting period value included in the digital audio signal; and an adder (112) for adding outputs from the phase comparator (110) and the detector (122) and for supplying a sum result as an oscillation control signal to the VCO (116).
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