发明公开
EP0097834A2 Circuits for accessing a variable width data bus with a variable width data field
失效
电路,用于访问数据总线与具有可变宽度的可变宽度数据字段。
- 专利标题: Circuits for accessing a variable width data bus with a variable width data field
- 专利标题(中): 电路,用于访问数据总线与具有可变宽度的可变宽度数据字段。
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申请号: EP83105439.0申请日: 1983-06-01
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公开(公告)号: EP0097834A2公开(公告)日: 1984-01-11
- 发明人: Dill, Frederick Hayes , Ling, Daniel Tajen , Matick, Richard Edward , McBride, Dennis Jay
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Blakemore, Frederick Norman (GB)
- 优先权: US394044 19820630
- 主分类号: G06F5/00
- IPC分类号: G06F5/00 ; G06F13/40
摘要:
A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N c and a data field of N f , the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. Structure includes a modulo N c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N c . A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.
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