@ A memory circuit provided with a control circuit which controls operations of the memory circuit in such a manner that the memory circuit is automatically set in a stand-by state when a value of a power voltage is reduced in absolute value irrespectively of a control signal from the outside and which consumes no DC current is disclosed. The control circuit comprises a load element coupled between first and second terminals, a series circuit of first and second field effect transistors coupled between the second terminal and a third terminal, the first transistor being controlled by the control signal, the second transistor being adapted to be conducting when a value of the power voltage is sufficient for allowing a normal access operation, a means for connecting the first terminal to one of the power voltage and a reference voltage, and a means for connecting the third terminal to the other of the power voltage and the reference voltage.