In a multiprocessor system buses each coupling a pair of processors (CPU) are serially arranged rectilinearly into a cluster bus arranged in one direction. All of these cluster buses are arranged in a plurality of directions (x, y, z) as a lattice pattern when viewed in plan. Each of the processors (CPU) supplies the respective cluster buses with send requests and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus so as to transfer data to the other processor on the cluster bus.