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公开(公告)号:EP0501474B1
公开(公告)日:2003-05-21
申请号:EP92103361.9
申请日:1992-02-27
申请人: Hitachi, Ltd.
发明人: Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Yamanaka, Hisayoshi , Okishima, Tetsuya , Kawabata, Kiyoshi
IPC分类号: H01L23/538 , H01L25/065
CPC分类号: H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
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公开(公告)号:EP0366017B1
公开(公告)日:1995-06-14
申请号:EP89119509.1
申请日:1989-10-20
申请人: HITACHI, LTD.
CPC分类号: G06F11/187
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公开(公告)号:EP0107191B1
公开(公告)日:1991-05-15
申请号:EP83110539.0
申请日:1983-10-21
申请人: HITACHI, LTD.
发明人: Mori, Kinji , Miyamoto, Shoji , Ihara, Hirokazu
IPC分类号: G05B19/417
CPC分类号: G05B19/41835 , Y02P90/083 , Y02P90/087 , Y02P90/12
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公开(公告)号:EP0103803A3
公开(公告)日:1986-08-20
申请号:EP83108742
申请日:1983-09-05
申请人: HITACHI, LTD.
CPC分类号: G06F13/378 , G06F13/4022 , G06F15/17343 , G06F15/80
摘要: In a multiprocessor system buses each coupling a pair of processors (CPU) are serially arranged rectilinearly into a cluster bus arranged in one direction. All of these cluster buses are arranged in a plurality of directions (x, y, z) as a lattice pattern when viewed in plan. Each of the processors (CPU) supplies the respective cluster buses with send requests and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus so as to transfer data to the other processor on the cluster bus.
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公开(公告)号:EP0147789A2
公开(公告)日:1985-07-10
申请号:EP84115865.2
申请日:1984-12-19
申请人: HITACHI, LTD.
发明人: Mori, Kinji , Miyamoto, Shoji , Ihara, Hirokazu
CPC分类号: H04L12/4637
摘要: Transmission line groups consisting of a plurality of loop-like transmission routes (1...5, 10...50, 100...500) are mutually connected via transmission controllers and are arranged in a two- or three-dimensional space. Processing units are thus connected as a homogeneous network in matrix or mesh form by means of the loop-like transmission routes The transmission controllers corresponding to the nodes (11...51) of the network have a communication management function such that they send the data without grasping the situation on the transmission routes, independently check the trouble between the adjacent transmission controllers, and specify the position of trouble. A communication network system such as a high local area network (LAN) or the like can be realized.
摘要翻译: 由多个环状传输路由(1 ... 5,10〜50,100 ... 500)组成的传输线路组经由传输控制器相互连接,并且被布置在二维或三维空间 。 因此,处理单元通过循环状传输路由以矩阵或网格形式连接成均匀网络。 对应于网络的节点(11 ... 51)的传输控制器具有通信管理功能,使得它们在不掌握传输路由的情况下发送数据,独立地检查相邻传输控制器之间的故障,并指定 烦恼的位置 可以实现诸如高局域网(LAN)等的通信网络系统。
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公开(公告)号:EP0541052B1
公开(公告)日:1996-02-07
申请号:EP92118870.2
申请日:1992-11-04
申请人: HITACHI, LTD.
CPC分类号: B64G4/00 , B64G1/1007 , B64G1/1085
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公开(公告)号:EP0146966B1
公开(公告)日:1994-09-07
申请号:EP84116339.7
申请日:1984-12-27
申请人: HITACHI, LTD.
发明人: Mori Kinji , Miyamoto, Shoji , Ihara, Hirokazu
CPC分类号: G06F15/8023 , H04L12/4637
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公开(公告)号:EP0501474A3
公开(公告)日:1993-01-13
申请号:EP92103361.9
申请日:1992-02-27
申请人: HITACHI, LTD.
发明人: Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Yamanaka, Hisayoshi , Okishima, Tetsuya , Kawabata, Kiyoshi
IPC分类号: H01L23/538 , H01L25/065
CPC分类号: H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要: An electronic circuit package having a wiring substrate (10), at least two semiconductor chips (101-106) and a bus line (100). All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
摘要翻译: 一种具有布线基板,至少两个半导体芯片和总线线路的电子电路封装。 通过总线连接的所有半导体芯片是封装在布线基板上的裸芯片,半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 总线包括两条数据总线,与一条数据总线相连的半导体芯片形成在布线基板的一侧,与另一条数据总线相连的半导体芯片形成在布线基板的另一侧。
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公开(公告)号:EP0366017A3
公开(公告)日:1991-06-12
申请号:EP89119509.1
申请日:1989-10-20
申请人: HITACHI, LTD.
CPC分类号: G06F11/187
摘要: The invention relates to an apparatus for rendering a plurality of sub-data processing systems to a fault tolerant system and a method for majority voting, wherein input signals supplied to the plurality of redundant subsystems are input to an output selecting circuit after an output of a subsystem is changed from an output signal of a subsystem having a most reliable output signal to another output signal of another subsystem having a lower reliable output signal in turn using self-diagnosis and cross-diagnosis in each subsystem according to majority voting rules. The output selecting circuit outputs a signal selected by the majority voting rules based on the output signals from the subsystems.
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公开(公告)号:EP0062333B1
公开(公告)日:1989-08-02
申请号:EP82102843.8
申请日:1982-04-02
申请人: Hitachi, Ltd.
发明人: Mori, Kinji , Ihara, Hirokazu
IPC分类号: G06F11/20
CPC分类号: H04L12/437 , G06F11/20 , G06F13/36 , G06F13/42
摘要: In a method of controlling a multicomputer system which includes a plurality of computers connected to a common transfer bus, each of the plurality of computers decides whether or not the adjacent computer is abnormal, and the computer which has decided that the adjacent computer is abnormal cuts off this adjacent computer from the transfer bus.
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