A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.