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公开(公告)号：EP0107395A3
公开(公告)日：1986-07-02
申请号：EP83305879
申请日：1983-09-29
申请人： FUJITSU LIMITED
发明人： Seki, Teruo , Yamauchi, Takahiko , Aoyama, Keizo
IPC分类号： G11C08/00 , H03K19/096
CPC分类号： G11C8/10
摘要： A decoder circuit receiving decoder inputs (A o to A m ) and producing decoder outputs (X 4 ). The decoder inputs are applied, as control inputs, to respective input transistors (P 70 to P 7m ) connected in parallel with each other. The outputs thereof are commonly connected to a node (Q). The node is provided with a gate transistor (N 70 ) and latch transistors (LT). The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.
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公开(公告)号：EP0100166A3
公开(公告)日：1986-02-12
申请号：EP83303915
申请日：1983-07-05
申请人： FUJITSU LIMITED
发明人： Yamauchi, Takahiko , Seki, Teruo , Aoyama, Keizo
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76895 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： in a semiconductor device including a connection structure comprising a first conductive layer 14 formed in or on a semiconductor substrate 11, a second conductive layer 15 arranged adjacent the first conductive layer 14, and a third conductive layer 17 connecting the first conductive layer 14, and to the second conductive layer 15. The third conductive layer 17 is in contact with the first 14 and second 15 conductive layers in a contact region 16'. One dimension of the portion of the second conductive layer 15 in the contact region 16' varies which enables the size of the contact region 16' to be reduced whilst still ensuring a positive connection between the first 14 and second 15, conductive layers even in the event of their misregistry.
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公开(公告)号：EP0087979A3
公开(公告)日：1986-01-08
申请号：EP83301104
申请日：1983-03-02
申请人： FUJITSU LIMITED
发明人： Aoyama, Keizo , Yamauchi, Takahiko , Seki, Teruo
CPC分类号： G11C5/063 , G11C5/005 , G11C5/14 , G11C11/4125 , H01L23/556 , H01L27/1112 , H01L2924/0002 , Y10S257/927 , H01L2924/00
摘要： A static-type semiconductor memory device having a three-layer structure; the gate-electrode wiring lines being formed by a first conductive layer of, for example, polycrystalline silicon; the word lines, the ground lines, and the power supply lines being formed by a second conductive layer of, for example, aluminum; and the bit lines being formed by a third conductive layer of, for example, aluminum; the bit lines extending in a column direction, and the ground lines extending in a row direction; whereby an improved integration degree, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles are attained.
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公开(公告)号：EP0090591A2
公开(公告)日：1983-10-05
申请号：EP83301617.3
申请日：1983-03-23
申请人： FUJITSU LIMITED
发明人： Aoyama, Keizo , Yamauchi, Takahiko , Seki, Teruo
CPC分类号： G11C7/1006 , G11C11/419
摘要： A semiconductor memory device comprising bit lines, word lines, memory cells arranged at the intersections of the bit lines and the word lines, data buses, and transfer gate transistors connected between the bit lines and the data buses, an information signal being read out to the data buses from the memory cells through the bit lines by turning on the transfer gate transistors and the transfer gate transistors having a threshold voltage smaller than that of the transistors used in the other circuits of the semiconductor memory device.
摘要翻译： 一种半导体存储器件，包括位线，字线，布置在位线和字线的交叉点处的存储单元，数据总线和连接在位线和数据总线之间的传输门晶体管，信息信号被读出 通过导通传输门晶体管和传输门晶体管从存储单元通过位线的数据总线，传输门晶体管的阈值电压小于半导体存储器件的其他电路中使用的晶体管的阈值电压。
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公开(公告)号：EP0330405B1
公开(公告)日：1992-07-08
申请号：EP89301628.7
申请日：1989-02-20
发明人： Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00215
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公开(公告)号：EP0107395B1
公开(公告)日：1990-02-21
申请号：EP83305879.5
申请日：1983-09-29
申请人： FUJITSU LIMITED
发明人： Seki, Teruo , Yamauchi, Takahiko , Aoyama, Keizo
IPC分类号： G11C8/00 , H03K19/096
CPC分类号： G11C8/10
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公开(公告)号：EP0330405A3
公开(公告)日：1989-11-02
申请号：EP89301628.7
申请日：1989-02-20
发明人： Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00215
摘要： A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.
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公开(公告)号：EP0149403A3
公开(公告)日：1988-03-30
申请号：EP84402759
申请日：1984-12-28
申请人： FUJITSU LIMITED
发明人： Seki, Teruo , Aoyama, Keizo
CPC分类号： G11C7/062 , G11C11/419
摘要： A sense amplifier for a circuit having a complementary output, such as a static MOS memory device, has a clamping means (0 7 , Q 8 ) connected between the output terminals (OUT1, OUT2) of the sense amplifier. The clamping means clamps the differential output voltage to a value which is sufficiently low to reduce the time delay of the output signal, in order to obtain a high switching rate of the sense amplifier, but still sufficient to keep the output voltage at the level necessary to operate a subsequent circuit of the device.
摘要翻译： 具有互补输出的电路（例如静态MOS存储器件）的读出放大器具有连接在读出放大器的输出端（OUT1，OUT2）之间的钳位装置（Q7，Q8）。 夹持装置将差分输出电压钳位到足够低的值以减小输出信号的时间延迟，以便获得感测放大器的高开关率，但仍足以将输出电压保持在必要的水平 以操作设备的后续电路。
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公开(公告)号：EP0083212A3
公开(公告)日：1985-12-04
申请号：EP82306893
申请日：1982-12-23
申请人： FUJITSU LIMITED
发明人： Yamauchi, Takahiko , Seki, Teruo , Aoyama, Keizo
IPC分类号： G06F11/20
CPC分类号： G11C29/846
摘要： A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which selects the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.
摘要翻译： 一种半导体存储器件，其中存储器单元以矩阵形式排列，并且其中当在存储器单元中存在缺陷单元并且选择包含缺陷单元的行或列时，选择的行或列被切换到预定的冗余 行或预定的冗余列额外和独立地提供。 提供了多个开关电路，每个开关电路连接到解码器电路的输出，该解码器电路选择存储器单元的行或列。 熔断电路连接到每个开关电路，并且当熔断电路中的熔断器断开时，含有缺陷单元的行或列切换到冗余行或冗余列。
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公开(公告)号：EP0089836A2
公开(公告)日：1983-09-28
申请号：EP83301539.9
申请日：1983-03-18
申请人： FUJITSU LIMITED
发明人： Aoyama, Keizo , Yamauchi, Takahiko , Seki, Teruo
IPC分类号： G11C5/00
CPC分类号： G11C11/417 , G11C5/145
摘要： A static-type semiconductor memory device includes peripheral circuits (20, 21), provided with at least a decoder, and memory cells (25). A high-voltage generating unit is provided in the chip so that a first power-source voltage (V cc ) supplied from an external unit is boosted to a second power source voltage level (V cc ) higher than said first power source voltage level. The first power-source voltage is supplied to the peripheral circuits and the second power-source voltage is supplied to the memory cells, thereby improving their stability in the presence of disturbances such as a-rays.
摘要翻译： 静态型半导体存储器件包括设置有至少解码器的外围电路（20,21）和存储单元（25）。 在芯片中设置有高电压产生单元，使得从外部单元提供的第一电源电压（Vcc）升高到高于所述第一电源电压电平的第二电源电压电平（Vcc）。 第一电源电压被提供给外围电路，并且第二电源电压被提供给存储器单元，从而在存在诸如α射线的干扰的情况下提高它们的稳定性。
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