Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).