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公开(公告)号：EP0109298A2
公开(公告)日：1984-05-23
申请号：EP83306931.3
申请日：1983-11-14
CPC分类号： G06F12/0607 , G11C11/407
摘要： Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).
摘要翻译： 选择逻辑（1）响应总线（19）上的22个地址位中的7个，通过提供信号SETRAS来选择模块，如果相同的行是连续两次是相同的行，则由信号PRECHG延迟。 SETRAS产生行地址选通RAS，识别信号ANYRAS，并且在延迟（11）之后，保持在锁存器（3）中的列地址信号CAS 16地址位被多路复用器8复用8位， 与RAS和CAS同步选择偶数和奇数存储器阵列（16和17）中的位置。 两个地址位和选择逻辑（20）在每个阵列中的四个平面之间进行选择。 存储器控制器响应识别信号ANYRAS以提供输出选通DOUTSTB-DOUTLTCH，以将两个读出的字输入到锁存器（7,8）中。 来自控制器DRVDOUTO，1的进一步信号（或者顺序地）两者之一（或两者都顺序地）使得一个或两个字被依次读出到数据总线（18）。
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公开(公告)号：EP0109298A3
公开(公告)日：1986-07-02
申请号：EP83306931
申请日：1983-11-14
CPC分类号： G06F12/0607 , G11C11/407
摘要： Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).
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公开(公告)号：EP0109298B1
公开(公告)日：1989-08-02
申请号：EP83306931.3
申请日：1983-11-14
CPC分类号： G06F12/0607 , G11C11/407
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公开(公告)号：EP0222520B1
公开(公告)日：1993-03-10
申请号：EP86308026.3
申请日：1986-10-16
CPC分类号： G06F13/378 , G06F11/10 , G06F13/4243
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公开(公告)号：EP0222520A3
公开(公告)日：1989-02-08
申请号：EP86308026.3
申请日：1986-10-16
CPC分类号： G06F13/378 , G06F11/10 , G06F13/4243
摘要： A computing system uses a system busy signal (SDBUSY) on its system bus to help control access to the bus. Each requester requiring access to the bus generates its internal request signal (SET REQ). One or more requesters can generate a request signal (SDREQX) on the bus when the system busy signal is not asserted (gate 74 and flip-flop 76). System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. Bus access is enabled by a signal (PRIORITY) only when all higher priority request signals (SDREQ1-SDREQX-1) are false (gate 72). A freeze signal (DRVFREZ) is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. These signals must be false before a requester with its request signal and priority signal tone can access the bus by putting an address signal thereon. The freeze signal may be generated by a memory control unit, a memory module or a requester.
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6.发明公开Bus access interface and method for a computer 失效在Reinner的Rezner，Schnittstelle und VerfahrenfürBuszugriff。
公开(公告)号：EP0222520A2
公开(公告)日：1987-05-20
申请号：EP86308026.3
申请日：1986-10-16
CPC分类号： G06F13/378 , G06F11/10 , G06F13/4243
摘要： A computing system uses a system busy signal (SDBUSY) on its system bus to help control access to the bus. Each requester requiring access to the bus generates its internal request signal (SET REQ). One or more requesters can generate a request signal (SDREQX) on the bus when the system busy signal is not asserted (gate 74 and flip-flop 76). System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. Bus access is enabled by a signal (PRIORITY) only when all higher priority request signals (SDREQ1-SDREQX-1) are false (gate 72). A freeze signal (DRVFREZ) is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. These signals must be false before a requester with its request signal and priority signal tone can access the bus by putting an address signal thereon. The freeze signal may be generated by a memory control unit, a memory module or a requester.
摘要翻译： 计算系统在其系统总线上使用系统忙信号（SDBUSY）来帮助控制对总线的访问。 需要访问总线的每个请求者产生其内部请求信号（SET REQ）。 当系统忙信号未被置位（门74和触发器76）时，一个或多个请求者可以在总线上产生请求信号（SDREQX）。 系统忙与请求信号一起被断言，并保持断言，直到产生请求信号的所有请求者已经以优先级顺序获得对总线的访问。 只有当所有较高优先级请求信号（SDREQ1-SDREQX-1）都为假（门72）时，总线访问才被信号（PRIORITY）使能。 在指令的地址相位期间，在系统总线上产生冻结信号（DRVFREZ），并且在指令的数据阶段的每次数据传输期间产生等待信号。 在具有请求信号和优先级信号音的请求者可以通过在其上放置地址信号来访问总线之前，这些信号必须是假的。 冻结信号可以由存储器控制单元，存储器模块或请求者产生。
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