An input buffer circuit having a source follower circuit composed of a first FET (Q 1 ) whose gate electrode has an input (V in ) connected thereto, and a second FET (Q 2 ) of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET (Qi) directly or through at least one level-shifting diode (D i ) and whose gate electrode is supplied with a control voltage (V cont ); and a FET inverter circuit (Q 3 , 0 4 ) which is connected to the drain electrode of the second FET directly or through at least one level-shifting diode (D 2 ); an output signal being derived from the FET inverter circuit (Q 3 , Q 4 ).