公开(公告)号：EP0378076A2

公开(公告)日：1990-07-18

申请号：EP90100043.0

申请日：1990-01-02

申请人： HITACHI, LTD.

发明人： Kamikawai, Ryotaro ,  Masaki, Akira

IPC分类号： H03K17/92 ,  H03K19/195

CPC分类号： H03K19/1952 ,  H03K17/92 ,  Y10S505/829 ,  Y10S505/861 ,  Y10S505/865

摘要： A switching circuit which comprises a digital circuit (11) formed of a superconductor, a transmission line (14) connected to the digital circuit (11) through magnetic coupling (12,13), and a resistor element (17) disposed in the transmission line (14) for differentiating the output of the digital circuit (11).

摘要翻译： 一种开关电路，包括由超导体形成的数字电路（11），通过磁耦合（12,13）连接到数字电路（11）的传输线（14）和布置在传输中的电阻元件（17） 线路（14），用于区分数字电路（11）的输出。

公开(公告)号：EP0110701B1

公开(公告)日：1987-09-30

申请号：EP83307239.0

申请日：1983-11-28

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Asano, Michio ,  Hayashi, Takehisa ,  Tanaka, Hirotoshi ,  Masaki, Akira

IPC分类号： H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

公开(公告)号：EP0110701A3

公开(公告)日：1985-01-09

申请号：EP83307239

申请日：1983-11-28

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Asano, Michio ,  Hayashi, Takehisa ,  Tanaka, Hirotoshi ,  Masaki, Akira

IPC分类号： H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

摘要： An input buffer circuit having a source follower circuit composed of a first FET (Q 1 ) whose gate electrode has an input (V in ) connected thereto, and a second FET (Q 2 ) of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET (Qi) directly or through at least one level-shifting diode (D i ) and whose gate electrode is supplied with a control voltage (V cont ); and a FET inverter circuit (Q 3 , 0 4 ) which is connected to the drain electrode of the second FET directly or through at least one level-shifting diode (D 2 ); an output signal being derived from the FET inverter circuit (Q 3 , Q 4 ).

公开(公告)号：EP0110701A2

公开(公告)日：1984-06-13

申请号：EP83307239.0

申请日：1983-11-28

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Asano, Michio ,  Hayashi, Takehisa ,  Tanaka, Hirotoshi ,  Masaki, Akira

IPC分类号： H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

摘要： An input buffer circuit having a source follower circuit composed of a first FET (Q 1 ) whose gate electrode has an input (V in ) connected thereto, and a second FET (Q 2 ) of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET (Qi) directly or through at least one level-shifting diode (D i ) and whose gate electrode is supplied with a control voltage (V cont ); and a FET inverter circuit (Q 3 , 0 4 ) which is connected to the drain electrode of the second FET directly or through at least one level-shifting diode (D 2 ); an output signal being derived from the FET inverter circuit (Q 3 , Q 4 ).

公开(公告)号：EP0193747B1

公开(公告)日：1991-01-16

申请号：EP86101516.2

申请日：1986-02-06

申请人： HITACHI, LTD.

发明人： Yamada, Minoru ,  Usui, Mitsuru Hitachi Yokohama Mitakeryo ,  Masaki, Akira ,  Nakanishi, Keiichirou Hitachi Daini Kyoshinryo ,  Tokuda, Masahide Hitachi Koyasudai Apartment House

IPC分类号： H01L23/46

CPC分类号： H01L24/83 ,  H01L23/3736 ,  H01L23/4332 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29191 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/0132

公开(公告)号：EP0378115A2

公开(公告)日：1990-07-18

申请号：EP90100171.9

申请日：1990-01-04

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

IPC分类号： G06F15/80

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

摘要翻译： 信息处理系统包括用于各个功能块（神经元）的输出的多个功能块（神经元）（100）和数据总线（300）。 功能块（神经元）之间的数据交换通过时分基础上的数据总线进行。 为了防止输出冲突或竞争，分别将地址分配给各个块（神经元），使得仅具有通过地址总线（302）提供的地址信号指定的自己的地址的功能块（神经元）输出数据 信号到数据总线上，而其他功能块（神经元）接收数据总线上的信息作为起始于在该时间点指定地址的功能块的信号。 地址顺序更改。 在一轮地址信号期间，数据从给定的功能块（神经元）发送到其他给定的功能块（神经元）。

公开(公告)号：EP0102643B1

公开(公告)日：1987-08-26

申请号：EP83108741.6

申请日：1983-09-05

申请人： HITACHI, LTD.

发明人： Asano, Michio ,  Masaki, Akira

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/13091 ,  H01L2924/14 ,  H03K19/00384 ,  H01L2924/00

公开(公告)号：EP0193747A3

公开(公告)日：1987-04-15

申请号：EP86101516

申请日：1986-02-06

申请人： HITACHI, LTD.

发明人： Yamada, Minoru ,  Usui, Mitsuru Hitachi Yokohama Mitakeryo ,  Masaki, Akira ,  Nakanishi, Keiichirou Hitachi Daini Kyoshinryo ,  Tokuda, Masahide Hitachi Koyasudai Apartment House

IPC分类号： H01L23/46

CPC分类号： H01L24/83 ,  H01L23/3736 ,  H01L23/4332 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29191 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/0132

摘要： @ Disclosed is a cooling structure cooling a multichip module for effectively removing heat generated from integrated circuit chips. A suction plate (30) formed with minute grooves (31) on one of its surfaces is disposed between each of the integrated circuit chip (2) and an associated cooling block (20) and is brought into contact at the grooved surface with the integrated circuit chip through a layer of a liquid (200) such as silicone oil interposed therebetween, thereby producing negative hydrostatic pressure by the capillary action of the grooves. The suction plate (30) has a thickness small enough to be bent under influence of the negative hydrostatic pressure to follow up warping of the integrated circuit chip, so that the clearance between the opposing surfaces of the suction plate and the integrated circuit chip can be minimized. An integrated circuit chip cooling device of surface-to-surface contact type operable with a low thermal resistance is provided, which can improve the maintainability and reliability without sacrificing the cooling efficiency.

公开(公告)号：EP0378115A3

公开(公告)日：1993-12-22

申请号：EP90100171.9

申请日：1990-01-04

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

IPC分类号： G06F15/80

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

公开(公告)号：EP0193747A2

公开(公告)日：1986-09-10

申请号：EP86101516.2

申请日：1986-02-06

申请人： HITACHI, LTD.

发明人： Yamada, Minoru ,  Usui, Mitsuru Hitachi Yokohama Mitakeryo ,  Masaki, Akira ,  Nakanishi, Keiichirou Hitachi Daini Kyoshinryo ,  Tokuda, Masahide Hitachi Koyasudai Apartment House

IPC分类号： H01L23/46

CPC分类号： H01L24/83 ,  H01L23/3736 ,  H01L23/4332 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29191 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/0132

摘要： @ Disclosed is a cooling structure cooling a multichip module for effectively removing heat generated from integrated circuit chips. A suction plate (30) formed with minute grooves (31) on one of its surfaces is disposed between each of the integrated circuit chip (2) and an associated cooling block (20) and is brought into contact at the grooved surface with the integrated circuit chip through a layer of a liquid (200) such as silicone oil interposed therebetween, thereby producing negative hydrostatic pressure by the capillary action of the grooves. The suction plate (30) has a thickness small enough to be bent under influence of the negative hydrostatic pressure to follow up warping of the integrated circuit chip, so that the clearance between the opposing surfaces of the suction plate and the integrated circuit chip can be minimized. An integrated circuit chip cooling device of surface-to-surface contact type operable with a low thermal resistance is provided, which can improve the maintainability and reliability without sacrificing the cooling efficiency.

摘要翻译： 公开了冷却多芯片模块的冷却结构，用于有效地去除集成电路芯片产生的热量。 在其一个表面上形成有微小凹槽（31）的吸板（30）设置在每个集成电路芯片（2）和相关联的冷却块（20）之间，并且在开槽表面处与集成 电路芯片通过介于其间的诸如硅油的液体（200）层，由此通过槽的毛细管作用产生负静压力。 吸板30的厚度足够小以在负静压力的影响下弯曲，以跟随集成电路芯片的翘曲，使得吸板和集成电路芯片的相对表面之间的间隙可以是 最小化。 提供了以低热阻可操作的表面接触型的集成电路芯片冷却装置，可以在不牺牲冷却效率的情况下提高可维护性和可靠性。