In a semiconductor memory device wherein a plurality of word lines and a plurality of bit lines (BL) are arranged perpendicular to each other, memory cells are located at the cross positions between each word line and each bitline, and one of the bit lines is selected by the operation of a bit line selection transistor driven with the signal of a column decoder via column selection signal lines (B 1 to B 8 ); the bit line selection transistors are separated into a plurality of blocks (31, 32, 33, 34) corresponding to each bit line group, the bit line selection transistors in each block are arranged along the direction of the bit lines, the gates of the bit line selection transistors are arranged perpendicular to the direction of the bitlines, and the gates of the bit line selection transistors in one block are commonly connected with the gates of the corresponding bit line selection transistors in the adjoining blocks. Thus, the pitch between transistor blocks is reduced, the pattern of the bit lines is made denser, and the integration density of the semiconductor memory device is increased.