利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.016 秒)

    Flash memory with improved erasability and its circuitry
    4.
    发明公开
    Flash memory with improved erasability and its circuitry 失效
    具有改进的可擦除性和电路的闪存

    公开(公告)号：EP0961289A2

    公开(公告)日：1999-12-01

    申请号：EP99115179.6

    申请日：1992-12-09

    申请人： FUJITSU LIMITED

    发明人： Akaogi, Takao ,  Kawashima, Hiromi ,  Takeguchi, Tetsuji ,  Hagiwara, Ryoji ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawamura, Shouichi ,  Ogawa, Yasushige

    IPC分类号： G11C16/06

    CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

    摘要： A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.

    摘要翻译： 一种闪速存储器，其包括：存储单元阵列（271），其中可以电擦除的多个非易失性存储单元被设置在阵列中，并且解码多个信号并访问所述存储单元阵列（271）的解码单元（273） 还包括：各包括第一电源端子（275）和第二电源端子（276）的驱动单元（274），输入解码单元（273）的输出，并且选择性地输出施加到第一电源 端子（275）或接近该电压的电压以及施加到第二电源端子的电压或接近该电压的电压; 驱动单元（274）呈现第一操作模式，其中向第一电源端子（275）施加第一电压并且向第二电源端子（276）施加低于第一电压的第二电压，以及以及 第二操作模式，其中向所述第一电源端子（275）施加第三电压，并且向所述第二电源端子（276）施加高于所述第三电压的第四电压; 并根据是否指定第一或第二操作模式来选择输出电压。

    Semiconductor memory device
    6.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0119002A2

    公开(公告)日：1984-09-19

    申请号：EP84300789.9

    申请日：1984-02-08

    申请人： FUJITSU LIMITED

    发明人： Yoshida, Masanobu ,  Itano, Kiyoshi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025

    摘要： In a semiconductor memory device wherein a plurality of word lines and a plurality of bit lines (BL) are arranged perpendicular to each other, memory cells are located at the cross positions between each word line and each bitline, and one of the bit lines is selected by the operation of a bit line selection transistor driven with the signal of a column decoder via column selection signal lines (B 1 to B 8 ); the bit line selection transistors are separated into a plurality of blocks (31, 32, 33, 34) corresponding to each bit line group, the bit line selection transistors in each block are arranged along the direction of the bit lines, the gates of the bit line selection transistors are arranged perpendicular to the direction of the bitlines, and the gates of the bit line selection transistors in one block are commonly connected with the gates of the corresponding bit line selection transistors in the adjoining blocks. Thus, the pitch between transistor blocks is reduced, the pattern of the bit lines is made denser, and the integration density of the semiconductor memory device is increased.

    摘要翻译： 在其中多个字线和多个位线（BL）彼此垂直布置的半导体存储器件中，存储器单元位于每个字线和每个位线之间的交叉位置处，并且一个位线是 通过由列选择信号线（B1至B8）以列解码器的信号驱动的位线选择晶体管的操作来选择; 位线选择晶体管被分成与每个位线组对应的多个块（31,32,33,34），每个块中的位线选择晶体管沿着位线的方向排列， 位线选择晶体管垂直于位线的方向布置，并且一个块中的位线选择晶体管的栅极共同与相邻块中的相应位线选择晶体管的栅极连接。 因此，晶体管块之间的节距减小，位线的图案更密集，并且半导体存储器件的集成密度增加。

    Integrated semiconductor circuit device for generating a switching control signal
    7.
    发明公开
    Integrated semiconductor circuit device for generating a switching control signal 失效
    用于产生切换控制信号的半导体集成电路器件。

    公开(公告)号：EP0116440A2

    公开(公告)日：1984-08-22

    申请号：EP84300648.7

    申请日：1984-02-02

    申请人： FUJITSU LIMITED

    发明人： Yoshida, Masanobu ,  Itano, Kiyoshi

    IPC分类号： G06F11/20 ,  G11C17/00

    CPC分类号： G11C29/789 ,  G11C29/83

    摘要： An integrated semiconductor circuit device for generating a switching control signal (BR1) including a fuse (611) having one terminal connected to a power source (V cc ), and the other terminal connected to a flip-flop circuit (614) comprising a cross-connected pair of complementary MOS field effect transistor type inverters (614a to 614d). The output of the flip-flop circuit (BR1) can be used as the switching control signal for a semiconductor memory device with a redundant circuit.

    Flash memory with improved erasability and its circuitry
    8.
    发明公开
    Flash memory with improved erasability and its circuitry 失效
    闪存具有更好的可擦和电路

    公开(公告)号：EP1168362A3

    公开(公告)日：2004-09-29

    申请号：EP01121238.8

    申请日：1992-12-09

    申请人： FUJITSU LIMITED

    发明人： Akaogi, Takao ,  Kawashima, Hiromi ,  Takeguchi, Tetsuji ,  Hagiwara, Ryoji ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawamura, Shouichi ,  Ogawa, Yasushige

    IPC分类号： G11C16/06 ,  H03K19/21 ,  G11C5/14

    CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

    摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.