A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest- order end of the counter (24), can be selectively inhibited by an inhibit word (M) to effectively vary the cycle period of the counter. The digital word (D) with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment (23) of the phase of the output timing pulse stream is effected by a controllable phase-locked loop (22).