公开(公告)号：EP0196167A3

公开(公告)日：1987-10-21

申请号：EP86301474

申请日：1986-02-28

申请人： TEKTRONIX, INC.

发明人： Sutton, Steven R. ,  Hoeren, Gerd H.

IPC分类号： G01R31/28 ,  G06F11/26 ,  H03K05/13

CPC分类号： G01R31/318307 ,  G01R31/31912 ,  H03K5/131 ,  H03K2005/00254

摘要： A method for adjusting a time delay of a signal with respect to a reference event comprises the steps of displaying a graphical representation of the delay time on a display terminal, modifying the displayed graphical depiction to indicate a different time delay, and then adjusting the time delay of the signal to match the modified time delay indicated by the displayed graphical depiction. The display terminal is controlled by a display controller and the graphical depiction of the delay time is modified by an operator using a first means to transmit a first indicating signal to the display controller and a second means to transmit a second indicating signal to the display controller. Each time the controller detects a first indicating signal, the graphically displayed delay time is incremented and each time the controller detects a second indicating signal, the graphically displayed delay time is decremented. The controller automatically adjusts the actual test signal delay time after the displayed delay time has been adjusted.

公开(公告)号：EP0096896A3

公开(公告)日：1984-09-05

申请号：EP83105868

申请日：1983-06-15

申请人： NEC CORPORATION

发明人： Ozawa, Takashi

IPC分类号： H03K05/13 ,  G11C07/00

CPC分类号： H03K5/131 ,  H03K2005/00078 ,  H03K2005/00195

摘要： A signal transmitting circuit which can transmit an input signal with a variable delay time is disclosed. The circuit comprises a series circuit of a transistor and a load element and a variable time constant circuit coupled to a control electrode of the transistor whose time constant value is changed in response to a control signal.

摘要翻译： 公开了一种能够传输具有可变延迟时间的输入信号的信号发送电路。 该电路包括晶体管和负载元件的串联电路和耦合到晶体管的控制电极的可变时间常数电路，其时间常数值响应于控制信号而改变。

公开(公告)号：EP0242721A3

公开(公告)日：1988-01-07

申请号：EP87105272

申请日：1987-04-09

申请人： NEC CORPORATION

发明人： Shibata, Kazuo

IPC分类号： H03K19/094 ,  H03K05/02 ,  H03K05/13

CPC分类号： H03K19/01714

摘要： An improved boot-strap type signal generating circuit having a small input capacitance and operable stably is disclosed. The signal generating circuit comprises a capacitor, a buffer circuit for generating a buffered signal in response to an input signal, the buffered signal being applied to one end of the capacitor, a delay circuit for generating a delayed signal of the buffered signal, the delayed signal being applied to the other end of the capacitor, and an output transistor having a gate connected to the one end of the capacitor.

公开(公告)号：EP0151875A3

公开(公告)日：1987-07-15

申请号：EP84308520

申请日：1984-12-07

申请人： FUJITSU LIMITED

发明人： Suzuki, Hirokazu c/o Fujitsu Ltd. ,  Akiyama, Takehiro c/o Fujitsu Ltd. ,  Morita, Teruo c/o Fujitsu Ltd. ,  Masunaga, Hikotaro ,  Takeda, Hirofumi

IPC分类号： H03K05/13

CPC分类号： H03K5/13 ,  G01R31/3191 ,  H03K19/086

摘要： A gate circuit device, for example for an integrated circuit tester (10, 20), for variably setting signal propagation delay time (Tpd), for example to control timings of various output signals delivered from the IC tester to an integrated circuit (11) to be tested to predetermined values, comprises a gate circuit having a pair of emitter coupled transistors (01, Q2) and a constant current source transistor (Q3) connected to the emitter side of the pair of transistors (Q1, Q2) and a terminal for applying a predetermined level of voltage (VC, Vs) to the base of the constant current source transistor (Q3) to control constant current (Figure 1). As an alternative (Figure 6) to such voltage control of signal propagation delay time, a current adjustment circuit (CONT) may be utilized to generate current in a constant current source transistor (e.g. Q35) in response to a control current (I CNT )· Thus, the gate circuot device controls signal propagation delay time by regulating either voltage or current in response to control current.

公开(公告)号：EP0131233A3

公开(公告)日：1987-02-04

申请号：EP84107673

申请日：1984-07-03

申请人： International Business Machines Corporation

发明人： Chang, Yihua E. ,  Grasso, Lawrence J. ,  Gruodis, Algirdas J. ,  Morgan, Carroll E.

IPC分类号： H03K05/13

CPC分类号： H03K5/156 ,  H03K3/78

摘要： A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest- order end of the counter (24), can be selectively inhibited by an inhibit word (M) to effectively vary the cycle period of the counter. The digital word (D) with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment (23) of the phase of the output timing pulse stream is effected by a controllable phase-locked loop (22).

公开(公告)号：EP0171022A3

公开(公告)日：1988-02-03

申请号：EP85109546

申请日：1985-07-30

申请人： Nippon Gakki Seizo Kabushiki Kaisha

发明人： Tomisawa, Norio

IPC分类号： H03K05/13 ,  G11B05/02

CPC分类号： H03K5/133 ,  G11B20/10009 ,  G11B20/225 ,  H03H11/265 ,  H03K3/0315 ,  H03K7/06 ,  H03K7/08 ,  H03K2005/00065 ,  H03K2005/00097 ,  H03K2005/00143 ,  H03K2005/00195

摘要： A signal delay device comprises a CMOS gate circuit (12, 14) having an input terminal (13) to which a binary input signal to be delayed is applied, an output terminal (15) from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means (16,18) is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

公开(公告)号：EP0145582A3

公开(公告)日：1987-08-05

申请号：EP84402441

申请日：1984-11-29

申请人： FUJITSU LIMITED

发明人： Mochizuki, Hirohiko ,  Miyahara, Hatsuo Dai-2 Yayoi-so 8 ,  Baba, Fumio Miyamaedaira Gurin Haitsu 48-303

IPC分类号： G11C05/00 ,  G11C08/00 ,  H03K05/13

CPC分类号： H03K5/133 ,  G11C5/00 ,  G11C8/18

摘要： A semiconductor device having a dynamic circuit (2) and a static circuit (3), wherein a clock signal (φ), in synchronization with the operation of the static circuit (3), initiates the operation of the dynamic circuit (2). A delay circuit (5) of a static type is provided to delay the clock signal (φ) and generate a delayed clock signal (φd). The delayed clock signal (φd) initiates to operate one stage of the dynamic circuit (2). As a result, the final-operating timing of the dynamic circuit (2) is substantially controlled by the delayed clock signal (φd), thereby matching the operation of the dynamic circuit (2) with the operation of the static circuit (3), regardless of the power supply voltage (V c c).

公开(公告)号：EP0003412A3

公开(公告)日：1979-09-05

申请号：EP79300087

申请日：1979-01-18

申请人： IMPERIAL CHEMICAL INDUSTRIES PLC

发明人： Kirby, Ian John ,  Mitchell, Michael Ian ,  Stratton, Andrew

IPC分类号： F42C01/06 ,  G01V01/08 ,  H03K05/13 ,  H03K05/15 ,  G04C23/46

CPC分类号： H03K5/131 ,  F42B3/122 ,  F42D1/055 ,  G01V1/08 ,  G04F1/005

摘要： Separate electrical timing and load activation devices are provided for each of plural electrical loads and each device is in use connected to receive reference timing signals from a remote central unit. Each of the separate timing and toad activation devices measures a reference time interval accurately defined by the reference timing signals and subsequently activates its associated electrical load after a respectively corresponding predetermined time delay which is determined as a function of the locally measured reference time interval. The time interval may advantageously be measured by counting locally generated clock pulses, for example, in an up-down counter which after counting the pulses between two reference timing signals reverses direction and activates the load when the count reaches the initial value. The devices are especially useful for firing electric fuseheads for blasting detonators in a predetermined delay sequence.

摘要翻译： 为多个电负载中的每一个提供单独的电定时和负载激活装置，并且每个装置被连接以从中央单元接收参考定时信号。 单独的定时和负载激活装置中的每一个测量由参考定时信号精确定义的参考时间间隔，并随后在根据本地测量的基准时间间隔确定的相应的预定时间延迟之后激活其相关联的电负载。

公开(公告)号：EP0181047A3

公开(公告)日：1988-01-13

申请号：EP85201805

申请日：1985-11-07

申请人： LSI LOGIC CORPORATION

发明人： Chan, Steven S.

IPC分类号： H03K05/13

CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K2005/00097 ,  H03K2005/00247

摘要： A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of present delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

公开(公告)号：EP0087707A3

公开(公告)日：1984-05-02

申请号：EP83101627

申请日：1983-02-21

申请人： Hewlett-Packard Company

发明人： Hardage, Phillip Kent ,  Peurifoy, Stephen W.

IPC分类号： H03K05/13

CPC分类号： H03K5/13

摘要： A pulse delay circuit uses a cascaded series of inverting elements with input thresholds to delay the transitions of an input pulse as it progresses through the series. The output of each inverter charges a capacitance in one polarity, but cannot discharge it. The discharge is achieved by current sources connected to the capacitors, charging them in a direction opposite to that of the inverter outputs. This produces a ramp which subsequently produces an abrupt transition aslhe ramp eventually crosses the input threshold. In this way every other inverter delays the leading edge, while the alternate intervening inverters delay the trailing edge. A final capacitance-tolerant inverting element with a threshold produces abrupt transitions for each transition as its input, to create a delayed replica of the input pulse. Asymmetries in the relative delay of the leading and trailing edges are corrected either by independently controlling one of the current sources or one of the thresholds.

摘要翻译： 脉冲延迟电路使用具有输入阈值的级联串联反相元件来延迟输入脉冲在其通过串联时的转变。 每个逆变器的输出以一个极性的电容充电，但不能放电。 放电是通过连接到电容器的电流源来实现的，它们以与反相器输出相反的方向进行充电。 这产生斜坡，随着斜坡最终跨越输入阈值，随后产生突然的转变。 以这种方式，每个其他逆变器延迟前沿，而交替的中间反相器延迟后沿。 具有阈值的最终电容容差反相元件为每个转换作为其输入产生突变，以产生输入脉冲的延迟复制。 通过独立地控制电流源中的一个或阈值之一来校正前沿和后沿的相对延迟中的不对称性。