A resistor personalized memory cell c(MC) consisting of a resistive gate field effect transistor (2). One end of the gate electrode (5) is connected to the memory cell access line (WL2), the other end to one of its source or drain regions (3, 4). The source or drain region (3, 4) not connected to the gate electrode (5) is connected to the memory cell bit line (BL2). Memory cell personalization is accomplished by selecting the resistance of the resistive gate (5). Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.