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公开(公告)号：EP0579924A1
公开(公告)日：1994-01-26
申请号：EP93108196.2
申请日：1993-05-19
IPC分类号： H01L23/538 , H01L21/66
CPC分类号： H01L22/22 , H01L23/5382 , H01L23/5384 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a high density electronic package is disclosed. The package (10) includes a module (12) of laminated semiconductor chips (14), including spare chip(s) and a supporting substrate (18) with a fixed interconnect pattern (20). Chip connection pads are provided at a first pad level of the module; one or more pads corresponding to each chip in the module (12). The module is tested at the first pad level to identify defective chip(s). A spare routing pattern is applied to the module for electrically isolating defective chip(s) and effectively substituting spare chip(s) therefor such that a predetermined pattern of metal interconnect landings (30) on an access surface of the module remains unchanged, as does the supporting substrate.
摘要翻译： 公开了一种制造高密度电子封装的方法。 封装（10）包括层叠半导体芯片（14）的模块（12），包括备用芯片和具有固定互连图案（20）的支撑衬底（18）。 芯片连接焊盘设置在模块的第一焊盘级; 一个或多个衬垫对应于模块（12）中的每个芯片。 在第一焊盘级别测试模块以识别有缺陷的芯片。 备用路由模式被应用于模块，用于电隔离有缺陷的芯片并且有效地代替其备用芯片，使得在模块的访问表面上的预定模式的金属互连着陆（30）保持不变，如 支撑基板。
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公开(公告)号：EP0137257B1
公开(公告)日：1989-01-25
申请号：EP84110056.3
申请日：1984-08-23
发明人： Bertin, Claude Louis
IPC分类号： H01L29/62 , H03K19/094
CPC分类号： H01L29/435 , H03K19/09441
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公开(公告)号：EP0139923A2
公开(公告)日：1985-05-08
申请号：EP84109398.2
申请日：1984-08-08
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C11/56 , G11C11/5692 , Y10S257/904
摘要： A resistor personalized memory cell c(MC) consisting of a resistive gate field effect transistor (2). One end of the gate electrode (5) is connected to the memory cell access line (WL2), the other end to one of its source or drain regions (3, 4). The source or drain region (3, 4) not connected to the gate electrode (5) is connected to the memory cell bit line (BL2). Memory cell personalization is accomplished by selecting the resistance of the resistive gate (5). Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.
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公开(公告)号：EP0644548A2
公开(公告)日：1995-03-22
申请号：EP94113742.4
申请日：1994-09-02
发明人： Bertin, Claude Louis , Howell, Wayne John , Hedberg, Erik Leigh , Kalter, Howard Leo , Kelley Jr., Gordon Arthur
IPC分类号： G11C5/00 , H01L25/065
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N × M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译： 一种集成存储器立方体结构和制造方法，其中通过控制逻辑芯片集成堆叠式半导体存储器芯片，使得利用单个更高级存储器芯片的功能外观来定义更强大的存储器架构。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，立方体的每个存储器芯片具有M个存储器设备。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有N×M个存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于促进存储器子单元的侧表面上的金属化图案化的方法。
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公开(公告)号：EP0644547A2
公开(公告)日：1995-03-22
申请号：EP94113741.6
申请日：1994-09-02
发明人： Bertin, Claude Louis , Howell,Wayne John , Hedberg, Erik Leigh , Kalter, Howard Leo , Kelley Jr., Gordon Arthur
IPC分类号： G11C5/00 , H01L25/065
CPC分类号： G11C5/06 , G11C5/04 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/85207 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2224/45099 , H01L2924/00
摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N × M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中通过控制逻辑芯片集成堆叠的半导体存储器芯片，从而通过单个更高级存储器芯片的外观来定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器设备。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有N×M个存储器件的单个存储器芯片架构出现在模块的I / O引脚处。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与构成子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于构成子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框架被固定到电接口层，并且控制逻辑芯片被固定到电接口层以驻留在引线框架内，从而产生致密的多芯片集成电路封装。 对应的制造技术包括用于促进存储器子单元的侧表面上的金属化图案化的方法。
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6.发明公开Thermally enhanced semiconductor chip package 失效Halbleiterchippackung mit verbesserterWärmeleitung。
公开(公告)号：EP0566913A1
公开(公告)日：1993-10-27
申请号：EP93105510.7
申请日：1993-04-02
发明人： Beilstein, Kenneth Edward , Bertin, Claude Louis , Kelley, Gordon Arthur, Jr. , Miller, Christopher Paul
IPC分类号： H01L23/473 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/473 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A structure and method is disclosed for cooling a semiconductor computer chip module (21). The semiconductor computer chip module is made up of a plurality of semiconductor chips bonded together. In one aspect of the present invention every other chip is staggered such that recesses are formed between protruding edges of every other chip along two opposite faces of the chip module. The opposite faces with the staggered chips are capped and sealed so that coolant channels are formed between the recesses and the sealing caps. In another aspect, one face of the chip module is bonded by a plurality of connectors to a base (23). The base and chip module with connectors form a chamber (29). The chamber is sealed and an opening (31) is made in the base to circulate coolant into and around the connectors of the base and up along the coolant channels which are in fluid communication with the base. Thermal vias are provided between selected connectors and the chip module to conduct heat from the chips of the module to the connectors.
摘要翻译： 公开了用于冷却半导体计算机芯片模块（21）的结构和方法。 半导体计算机芯片模块由多个结合在一起的半导体芯片组成。 在本发明的一个方面，每隔一个芯片交错，使得在芯片模块的两个相对面上的每个其它芯片的突出边缘之间形成凹槽。 具有交错的芯片的相对面被封盖和密封，使得在凹部和密封盖之间形成冷却剂通道。 另一方面，芯片模块的一个面通过多个连接器连接到基座（23）。 具有连接器的基座和芯片模块形成腔室（29）。 腔室被密封，并且在基座中形成开口（31），以使冷却剂沿着与底座流体连通的冷却剂通道使冷却剂循环到基座的连接器内和周围。 在选定的连接器和芯片模块之间提供热通孔，以将热量从模块的芯片传导到连接器。
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公开(公告)号：EP0048814A2
公开(公告)日：1982-04-07
申请号：EP81106437.7
申请日：1981-08-19
IPC分类号： G11C11/00
CPC分类号： H01L29/7882 , G11C14/00 , H01L27/115
摘要： This invention provides improved non-volatile semiconductor memories which include a volatile circuit (10) coupled to a non-volatile device (22) having a floating gate (28) and first and second control gates (34, 36 & 38, 40) capacitively coupled to the floating gate (28) with a charge injector structure (40) disposed between the floating gate and one of the two control gates. The volatile circuit may be a dynamic one-device cell such as a conventional flip-flop or latch cell.
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8.发明公开Statische Speicherzelle aus zwei Feldeffekttransistoren und Verwendung derselben in einem programmierfähigen logischen Schaltungsverband 失效静态存储单元包括两个场效应晶体管，和在能够敷料的编程电路使用相同的逻辑。
公开(公告)号：EP0002486A1
公开(公告)日：1979-06-27
申请号：EP78101565.6
申请日：1978-12-05
发明人： Bertin, Claude Louis
CPC分类号： H01L27/11 , G11C7/20 , H01L29/435 , H03K3/356 , H03K3/35606 , Y10S257/904
摘要： Es wird eine statische Speicherzelle aus zwei Feldeffekttransistoren beschrieben, deren Elektroden untereinander und/oder mit Ansteuer-, Ein- und Ausgangsleitungen in einen Speicherzellenverband oder in einer Anordnung aus vielen steuerbaren logischen Schaltungen in Verbindung stehen, wobei die Feldeffekttransistoren der Speicherzelle mit einer als Widerstand ausgebildeten Gate-Elektrode ausgerüstet sind. Das als Widerstand ausgebildete Gate ist über dem Kanalbereich angeordnet und trennt die Source-, Drain-Diffusionen voneinander, die aus polykristallinem Silicium mit hohem Widerstandswert bestehen.
摘要翻译： 它是由两个场效应晶体管静态存储器单元，其中所述电极是彼此描述和/或与致动，在存储器单元关联或在连接的许多可控逻辑电路的布置的输入和输出线，所述形成所述存储器单元的场效应晶体管与电阻 设置栅电极。 所形成的电阻栅极设置在所述沟道区和分离所述源极，漏极彼此的扩散，其由具有高电阻值的多晶硅。
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公开(公告)号：EP0757431A2
公开(公告)日：1997-02-05
申请号：EP96305180.0
申请日：1996-07-15
IPC分类号： H02N1/00
CPC分类号： H01H1/0036 , H02N1/004
摘要： Machine structures each comprising a stack of a plurality of micromachine layers laminated together are presented, along with fabrication methods therefore. Each machine structure includes a movable member(s) defined from microstructure of at least one layer of the plurality of micromachine layers comprising the stack. During fabrication, the micromachine layers are separately formed using VLSI techniques and then subsequently laminated together in a selected arrangement in the stack to define the machine structure.
摘要翻译： 因此呈现了各自包括层压在一起的多个微机械层的堆叠的机器结构以及制造方法。 每个机器结构包括由构成堆叠的多个微机械层中的至少一层的微结构限定的可移动构件。 在制造期间，使用VLSI技术分别形成微型机械层，然后随后以堆叠中的选定布置将其一起层压以限定机器结构。
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公开(公告)号：EP0644548A3
公开(公告)日：1995-07-12
申请号：EP94113742.4
申请日：1994-09-02
发明人： Bertin, Claude Louis , Howell, Wayne John , Hedberg, Erik Leigh , Kalter, Howard Leo , Kelley Jr., Gordon Arthur
IPC分类号： G11C5/00 , H01L25/065
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N × M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
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