A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array (70) of cells (71) consisting of nearest neighbour connected gated full adders. The cells (71) multiply data bits received from laterally adjacent cells (70) and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell (71) below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array (70). An adder tree (110) accumulates non-simultaneously computed contributions to individual output terms. The tree (110) incorporates a delay (122) and switches (120, 121) arranged to implement or bypass the delay (122) according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.