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    Digital data processor for multiplying data elements by coefficients
    2.
    发明公开
    Digital data processor for multiplying data elements by coefficients 失效
    数字数据处理器，用于通过系数数据元素进行数据处理

    公开(公告)号：EP0144123A3

    公开(公告)日：1986-03-19

    申请号：EP84306215

    申请日：1984-09-10

    申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION

    发明人： McCanny, John Vincent Dept. of Elect. & Electronic ,  McWhirter, John Graham ,  Wood, Kenneth William

    IPC分类号： G06F15/347

    CPC分类号： G06F15/8046 ,  G06F17/15

    摘要： A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array (70) of cells (71) consisting of nearest neighbour connected gated full adders. The cells (71) multiply data bits received from laterally adjacent cells (70) and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell (71) below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array (70). An adder tree (110) accumulates non-simultaneously computed contributions to individual output terms. The tree (110) incorporates a delay (122) and switches (120, 121) arranged to implement or bypass the delay (122) according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

    Digital data processor for multiplying data elements by coefficients
    4.
    发明公开
    Digital data processor for multiplying data elements by coefficients 失效
    相乘数据元素和系数的数字数据处理器。

    公开(公告)号：EP0144123A2

    公开(公告)日：1985-06-12

    申请号：EP84306215.9

    申请日：1984-09-10

    申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION

    发明人： McCanny, John Vincent Dept. of Elect. & Electronic ,  McWhirter, John Graham ,  Wood, Kenneth William

    IPC分类号： G06F15/347

    CPC分类号： G06F15/8046 ,  G06F17/15

    摘要： A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array (70) of cells (71) consisting of nearest neighbour connected gated full adders. The cells (71) multiply data bits received from laterally adjacent cells (70) and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell (71) below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array (70). An adder tree (110) accumulates non-simultaneously computed contributions to individual output terms. The tree (110) incorporates a delay (122) and switches (120, 121) arranged to implement or bypass the delay (122) according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

    Integrated data processing circuits
    6.
    发明公开
    Integrated data processing circuits 失效
    Integrierte Datenverarbeitungsschaltungen。

    公开(公告)号：EP0073116A2

    公开(公告)日：1983-03-02

    申请号：EP82304165.2

    申请日：1982-08-06

    申请人： NATIONAL RESEARCH DEVELOPMENT CORPORATION

    发明人： McCanny, John Vincent ,  McWhirter, John Graham ,  Wood, Kenneth William

    IPC分类号： G06F7/52 ,  G06F15/347 ,  G06F15/332 ,  G06F15/336

    CPC分类号： G06F7/5306 ,  G06F7/49994 ,  G06F7/5443 ,  G06F15/8023 ,  G06F17/145 ,  G06F17/15 ,  G06F2207/3836 ,  G06F2207/388 ,  G06F2207/3892

    摘要： The invention provides a digital data processor which has been systemetised down to bit level.
    The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency.
    Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers.
    Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.

    摘要翻译： 本发明提供了一种已经被系统化到位级的数字数据处理器。 处理器包括对输入位执行逻辑运算的相同处理单元的规则阵列。 单元在控制数据位的输入和从单元输出的时钟的控制下重复执行单元操作。 每个位在具有最高重复频率的时钟的一次重复中最多参与最多一个小区操作。 用于处理较大数字的处理单元阵列可以从用于较小数字的较小阵列容易地构建。 已经获得了一种类型的处理单元的完全工作的设计，证明了由多个单元组成的整个阵列。