发明公开
EP0146789A2 Process for forming isolating trenches in integrated circuit devices
失效
一种用于集成电路器件的制备隔离沟槽的过程。
- 专利标题： Process for forming isolating trenches in integrated circuit devices
- 专利标题（中）： 一种用于集成电路器件的制备隔离沟槽的过程。
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申请号： EP84114122.9申请日： 1984-11-23
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公开(公告)号： EP0146789A2公开(公告)日： 1985-07-03
- 发明人: Goth, George Richard , Hansen, Thomas Adrian , Villetto, Robert Thomas, Jr.
- 申请人： International Business Machines Corporation
- 申请人地址： Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构： Rudack, Günter O., Dipl.-Ing.
- 优先权： US566593 19831229
- 主分类号： H01L21/308
- IPC分类号： H01L21/308 ; H01L21/306 ; H01L21/76
摘要：
A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation.
This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.
This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.
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