In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).