公开(公告)号：EP0161947B1

公开(公告)日：1991-07-31

申请号：EP85400383.7

申请日：1985-02-28

申请人： FUJITSU LIMITED

发明人： Kunitoki, Tadayoshi ,  Gotoh, Kunihiko

IPC分类号： G11C17/00 ,  G11C17/16

CPC分类号： G11C17/16

公开(公告)号：EP0213954A3

公开(公告)日：1989-10-18

申请号：EP86306774.0

申请日：1986-09-02

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H03M1/40 ,  H03M1/02 ,  G06G7/14

CPC分类号： H03M1/162 ,  H03M1/442

摘要： In an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value, the circuit comprises at least two analog processing units (11A, 11B) providing conversion hold blocks. Each of the analog processing units (11A, 11B) has two functions, that is, one function is to perform sampling of an analog value and to circularly convert the analog value to an output analog value in order to obtain a digital value based on the output analog value by a cyclic A/D conversion method, and the other function is to sequentially input digital codes and to convert digital codes in order to obtain an analog value.

公开(公告)号：EP0194134A2

公开(公告)日：1986-09-10

申请号：EP86301537.6

申请日：1986-03-05

申请人： FUJITSU LIMITED

发明人： Kousaka, Kunimitsu ,  Gotoh, Kunihiko

IPC分类号： H03K19/094

CPC分类号： H03K19/0948 ,  H03K19/018521

摘要： @ A semiconductor integrated circuit including: an inverter circuit (1) including first and second transistors (T 7 , T 8 ) of different conductivities, and a level shift circuit (2), the first transistor (T 7 ) being supplied with an input signal (IN) via the level shift circuit (2), the second transistor (T 8 ) being supplied with the input signal (IN) directly, and the level shift circuit (2) having an amount of level shift such that, when an input signal (IN) corresponding to an «H» logic level is received, the level of the input signal supplied via the level shift circuit (V A ) is shifted near to the threshold level of the first transistor (T 7 ), to ensure correct switching of the first transistor (T 7 ). The level shift circuit (2) may be formed by a level divider circuit (T 1 , T 2 , T 3 ) and a source follower circuit (T 4 , T 5 ).

公开(公告)号：EP1607764A1

公开(公告)日：2005-12-21

申请号：EP05004799.2

申请日：2005-03-04

申请人： FUJITSU LIMITED

发明人： Tanaka, Yoshinori ,  Gotoh, Kunihiko ,  Yamazaki, Daisuke

IPC分类号： G01S13/75 ,  G01S13/76 ,  G06K19/07

CPC分类号： G06K7/0008 ,  G01S13/758 ,  G06K7/10297 ,  G06K19/0723 ,  Y02D70/10

摘要： A reader device (100) and RF tag (400) improves the efficiency of frequency usage without increasing bandwidth using wireless communication from the reader to the tag and provides a transmission method that improves the power supply efficiency from the reader to the tag to extend the communication distance from the tag to the reader. A reader device for wirelessly communicating with an RF tag, comprises circuitry operable to transmit a wireless signal including information indicating encoding method of data to the RF tag and circuitry operable to receive and demodulate a wireless signal from the RF tag.

摘要翻译： 读取器设备（100）和RF标签（400）提高频率使用的效率，而不用增加使用从读取器到标签的无线通信的带宽，并提供一种传输方法，其提高从读取器到标签的电源效率， 从标签到阅读器的通信距离。 一种用于与RF标签无线通信的读取器装置，包括可操作以将包括指示数字的编码方式的信息的无线信号发射到RF标签的电路和可操作以从RF标签接收和解调无线信号的电路。

公开(公告)号：EP0372956B1

公开(公告)日：1995-08-23

申请号：EP89312758.9

申请日：1989-12-07

申请人： FUJITSU LIMITED

发明人： Yoshikawa, Yoshinori ,  Gotoh, Kunihiko

IPC分类号： G05F3/20

CPC分类号： G05F3/20

公开(公告)号：EP0318396A3

公开(公告)日：1990-03-21

申请号：EP88402978.6

申请日：1988-11-25

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H03F1/30

CPC分类号： H03F1/308

摘要： An operational amplifier circuit comprises a differential amplifier circuit (1) for generating an output voltage (V₂) in response to the difference in potential between two input signals (+IN, -IN), a level shift circuit (2) for shifting the output voltage of the differential amplifier circuit, a push-pull output circuit (3) which operates in response to the output voltages of the differential amplifier circuit and the level shift circuit, and a bias circuit (4) for gen­erating a bias voltage (V B ) in response to a power supply voltage (V DD ) to control the level shift circuit. The output voltage of the level shift circuit is not affected by fluctuations of the power supply voltage.

公开(公告)号：EP0192456A3

公开(公告)日：1989-04-05

申请号：EP86301107.8

申请日：1986-02-18

申请人： FUJITSU LIMITED

发明人： Saito, Tadahiro ,  Gotoh, Kunihiko

IPC分类号： H04M1/24 ,  H04M1/50 ,  H04M1/31 ,  G01R31/28

CPC分类号： H04M1/24 ,  H04M1/312 ,  H04M1/50

摘要： In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).

摘要翻译： 在包括内部电路（9）的半导体集成电路（10）中，当内部电路以通常模式工作时产生用于操作内部电路（9）的基本时钟信号的振荡电路（1），一对端子 （Toscin，Toscout），分别连接到振荡电路（1）的输入侧和输出侧;振荡器（8），当内部电路（9）接通时，连接在上述一对端子（Toscin，Toscout） 以正常模式操作;复位端子（Treset），通过该复位端子将用于复位内部电路的复位信号从集成电路（10）外部提供给内部电路;以及测试电路（3,4,5），用于操作 内部电路（9）处于测试模式; 当预定电平的信号从芯片的外部提供给测试电路时，测试电路通过上述一对端子（Toscout）中的一个将从集成电路外部测试的时钟信号提供给内部电路（9） 上述一对端子中的另一个（Toscin）和复位端子（Treset）中的每一个。

公开(公告)号：EP0280123A1

公开(公告)日：1988-08-31

申请号：EP88102025.9

申请日：1988-02-11

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H04N5/18

CPC分类号： H04N5/185

摘要： A voltage level setting circuit sets a voltage level of a predetermined portion of an input signal received through a coupling capacitor (C2) to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit system, where the voltage level of the predetermined portion is used as a reference level of the input signal. The voltage level setting circuit comprises a charge injecting circuit (23, 43, 63) for injecting a quantity of charge to a node (N) between the coupling capacitor and the signal processing circuit system, and a control circuit (31-34, 73-75) for controlling the injection of charge by the charge injecting circuit responsive to a signal from the signal processing circuit system so that the voltage level of the predetermined portion at the node is set to the desired reference voltage level.

摘要翻译： 电压电平设定电路将通过耦合电容器（C2）接收的输入信号的预定部分的电压电平设置为适合在信号处理电路系统中执行的信号处理的期望参考电压电平，其中电压 预定部分的电平被用作输入信号的参考电平。 电压电平设定电路包括用于向耦合电容器和信号处理电路系统之间的节点（N）注入一定量的电荷的电荷注入电路（23,43,63），以及控制电路（31-34,73 -75），用于响应于来自信号处理电路系统的信号，通过电荷注入电路控制电荷注入，使得节点处的预定部分的电压电平被设置为期望的参考电压电平。

公开(公告)号：EP0257878A2

公开(公告)日：1988-03-02

申请号：EP87306975.1

申请日：1987-08-06

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Shimizu, Yoshiaki ,  Gotoh, Kunihiko

IPC分类号： H03M1/66 ,  H03M1/10

CPC分类号： H03M1/1061 ,  H03M1/667 ,  H03M1/806

摘要： A D/A converter, especially a cyclic type D/A converter, having an error detection and correction system including: a code conversion circuit (101) for converting a binary code (C) to a multi-states code; a digital-to-analog conversion circuit (102) connected to the code conversion circuit (101) for converting the multi-states code to an analog value; a detection circuit (103) operatively connected to the digital-to-analog conversion circuit for converting the analog value to a digital code; and a control circuit (104) operatively connected to the code conversion circuit (101), digital-to analog conversion circuit (102) and detection circuit (103) for calculating a voltage difference between the analog value at a predetermined code value and another analog value adjacent to the predetermined code value, and for calculating a differential non-linearity error from the voltage difference based on the digital code, in order to obtain error and correction values of capacitors forming the digital-to-analog conversion circuit.

摘要翻译： 一种具有错误检测和校正系统的D / A转换器，特别是循环型D / A转换器，包括：用于将二进制代码（C）转换成多状态代码的代码转换电路（101） 连接到代码转换电路（101）的数模转换电路（102），用于将多状态代码转换为模拟值; 检测电路（103），可操作地连接到所述数模转换电路，用于将所述模拟值转换成数字代码; 以及可操作地连接到代码转换电路（101）的控制电路（104），数模转换电路（102）和检测电路（103），用于计算预定代码值的模拟值与另一模拟电路之间的电压差 值，并且用于基于数字码从电压差计算差分非线性误差，以便获得形成数模转换电路的电容器的误差和校正值。

公开(公告)号：EP0254323A2

公开(公告)日：1988-01-27

申请号：EP87110760.3

申请日：1987-07-24

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H03F3/45

CPC分类号： H03F3/45076

摘要： A differential amplifier circuit whereby a recovery time produced due to large amplitude of a voltage difference appearing between differential input signals (Sl, S2) fed to a differential input stage of the differential amplifier circuit is shortened by adding two transistors (Tlʹ, T2ʹ) to an ordinary differential amplifier circuit (Tl, T2) so that the two transistors (Tlʹ, T2ʹ) are connected with nodes (Nl, N2) at which two transistors (Tl, T2) of the differential input stage are connected with two loads (T3, T4) of the differential input stage, respectively. the one (Tlʹ) of the two added transistors (Tlʹ, T2ʹ) directly contributes to shorten the recovery time by reducing a voltage at one of the nodes (N2) from which an output signal voltage of the differential amplifier circuit is obtained, and the other (T2ʹ) of the two added transistors is for obtaining symmetric property of the differential amplifier circuit.

摘要翻译： 差分放大器电路，通过将两个晶体管（T1'，T2'）相加，从而缩短由馈送到差分放大器电路的差分输入级的差分输入信号（S1，S2）之间出现的电压差大幅度产生的恢复时间 ）到普通差分放大器电路（T1，T2），使得两个晶体管（T1'，T2'）与差分输入级的两个晶体管（T1，T2）连接的节点（N1，N2）连接 分别为差分输入级的两个负载（T3，T4）。 两个添加的晶体管（T1'，T2'）中的一个（T1'）直接有助于通过减少获得差分放大器电路的输出信号电压的节点（N2）之一处的电压来缩短恢复时间 ，并且两个相加的晶体管的另一个（T2'）用于获得差分放大器电路的对称性质。