An arithmetic unit with a simple overflow detection system performs arithmetic operations between first and second data. The first data is exclusively divided into a fixed value portion and a variable portion whose digit position is lower than that of the fixed value portion. A ratio of a bit length of the fixed value portion to that of the variable portion in the first data varies. The second data corresponds to only the variable portion of the first data. The arithmetic unit includes an adder (40) for adding the first and second data in their entire lenghts, switch circuits (50, 60) for separating output data from the first data and the adder (40) into fixed value and variable portions, a comparator (70) for comparing the fixed value portions of the outputs from the first data and the adder (40) and outputting a coincidence or noncoincidence signal, an output register (80) for linking the fixed value portion of the first data and the variable portion of the output from the adder (40) and outputting the linked data, and an overflow detector (90) for detecting an overflow in response to the noncoincidence signal from the comparator (70).