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    INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS
    1.
    发明公开
    INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS 审中-实审

    公开(公告)号：EP4325350A3

    公开(公告)日：2024-05-15

    申请号：EP23213442.9

    申请日：2019-02-28

    Applicant: Intel Corporation

    Inventor： DAS, Dipankar ,  MELLEMPUDI, Naveen K. ,  DUTTA, Mrinmay ,  KUMAR, Arun ,  MUDIGERE, Dheevatsa ,  KUNDU, Abhisek

    IPC: G06F7/48 ,  G06F9/30

    CPC classification number: G06F7/483 ,  G06F2207/38220130101 ,  G06F9/30036 ,  G06F9/30065 ,  G06N3/063 ,  G06F9/30014 ,  G06F7/5443 ,  G06F9/3887

    Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor comprises: fetch circuitry to fetch a single multiply-accumulate (MAC) instruction having fields to indicate an opcode, a destination, a first source vector having a first element width, and a second source vector having a second element width that is smaller than the first element width; decode circuitry to decode the fetched single MAC instruction; and a single instruction multiple data (SIMD) execution circuit to execute the single MAC instruction and perform multiply-accumulate operations within each processing lane of a plurality of processing lanes, the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane, the result data element each having a width greater than the first element width and the second element width.

    INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS
    2.
    发明公开
    INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS 审中-公开

    公开(公告)号：EP4325350A2

    公开(公告)日：2024-02-21

    申请号：EP23213442.9

    申请日：2019-02-28

    Applicant: Intel Corporation

    Inventor： DAS, Dipankar ,  MELLEMPUDI, Naveen K. ,  DUTTA, Mrinmay ,  KUMAR, Arun ,  MUDIGERE, Dheevatsa ,  KUNDU, Abhisek

    IPC: G06F7/48

    Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor comprises: fetch circuitry to fetch a single multiply-accumulate (MAC) instruction having fields to indicate an opcode, a destination, a first source vector having a first element width, and a second source vector having a second element width that is smaller than the first element width; decode circuitry to decode the fetched single MAC instruction; and a single instruction multiple data (SIMD) execution circuit to execute the single MAC instruction and perform multiply-accumulate operations within each processing lane of a plurality of processing lanes, the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane, the result data element each having a width greater than the first element width and the second element width.

    TISSUE DISORDER IMAGING ANALYSIS
    7.
    发明授权
    TISSUE DISORDER IMAGING ANALYSIS 有权
    组织疾病成像分析

    公开(公告)号：EP1595205B1

    公开(公告)日：2018-04-25

    申请号：EP03781439.9

    申请日：2003-10-28

    Applicant: THE GENERAL HOSPITAL CORPORATION

    Inventor： SORENSEN, Gregory, A. ,  MENEZES, Nina, M. ,  AY, Hakan

    IPC: G06F19/00 ,  G06F7/48

    CPC classification number: A61B5/7275 ,  A61B5/0042 ,  A61B5/055 ,  A61B5/4064 ,  A61B5/4076 ,  A61B5/4088 ,  A61B5/4842 ,  A61B5/4848 ,  A61B6/032 ,  G06F19/00 ,  G06F19/321 ,  G06F19/324 ,  G06T7/0014 ,  G16H50/70

    Abstract: A method is described for determining the efficacy of a treatment method for a patient having a tissue disorder by administering a treatment to the patient, measuring a hazard score at two or more points in time after administering the treatment by obtaining an image of a tissue of the patient, wherein the image comprises a plurality of patient image voxels, identifying voxels of the patient image that are damaged by the disorder as damaged patient image voxels, obtaining a hazard atlas of the disorder in the tissue, wherein the hazard atlas comprises a plurality of voxels, each voxel representing a hazard value of an extent of deficit caused by damage from the disorder to that voxel of tissue at that location, and computing a hazard score for the patient, wherein the score is the integration of all damaged patient image voxels weighted by a hazard value corresponding to that voxel location, wherein the hazard score determines the patient's prognosis, and determining the efficacy of the treatment based on the hazard scores. Further, a hazard atlas and methods for generating a hazard atlas are described.

    FIXED-POINT MULTIPLICATION BY ONE
    8.
    发明公开
    FIXED-POINT MULTIPLICATION BY ONE 审中-公开
    MITLIPLITIZIERUNG在FIXPUNKT MIT DEM WERT EINS

    公开(公告)号：EP3035188A1

    公开(公告)日：2016-06-22

    申请号：EP15196356.8

    申请日：2015-11-25

    Applicant: AptCore Ltd

    Inventor： WILDMAN, Leon ,  STYLES, Timothy

    IPC: G06F7/48 ,  G06F7/499

    CPC classification number: G06F7/49942 ,  G06F7/4806 ,  G06F2207/3808

    Abstract: A signal processing apparatus (10) comprises: a fixed-point compute unit (30) for operating on fractional 2's complement values without a mantissa; a memory unit (26) for storing a constant complex value to be used by the compute unit (30) to perform a complex arithmetic operation and a mapping unit (62), the mapping unit (62) being configured to map a complex value stored by the memory unit having a particular imaginary component, such as -1, to a value of unity, i.e. +1.

    Abstract translation: 信号处理装置（10）包括：用于在没有尾数的情况下对小数2的补码进行操作的定点计算单元（30） 存储单元（26），用于存储要由计算单元（30）使用以执行复数运算的常数复数值和映射单元（62），所述映射单元（62）被配置为映射存储的复数值 由具有特定虚部（例如-1）的存储单元提供为1的值，即+1。

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