A phase-locked digital synthesiser comprises a voltage-­controlled oscillator (6) supplying a frequency divider (7) the output of which is fed to a phase-sensitive detector (9) also receiving an input from a reference oscillator (10). The output of the detector (9) is fed back by a feedback loop to the voltage-controlled oscillator (6) to achieve phase-locking. The divider (7) receives an input from a logic circuit (8) to control the division ratio of the divider (7), the logic circuit being prompted by a control signal which is also used to select one of a plurality of loop filters (12,13) connected for selectable use in the feedback loop from the detector (9) to the voltage controlled oscillator (6), the selected loop filter being appropriate to the prompted division ratio. Other embodiments include compensating means to correct a loop phase error arising from a change in the division ratio.