A data reading circuit for a semiconductor memory device includes: a first input terminal and a second input terminal for receiving complementary signals (DB, DB ); a first (12) and a second (11) current mirror type sense amplifiers, each of the current mirror type sense amplifiers including: a reference node (N1, N2); an output terminal; a first transistor (Q3, Q8) connected with the reference node (N1, N2); and a second transistor (Q4, Q9) connected with the output terminal. The gates of the first transistor (Q3) of a first sense amplifier (12) and of the second transistor (Q4) of a second sense amplifier (11) are connected to the first input terminal and the gates of the second transistor (Q4) of the first sense amplifier (12) and of the first transistor (Q8) of the second sense amplifier (11) are connected to the second input terminal. A first short-circuiting transistor (71) is connected between the reference nodes (N1, N2) and able to conduct temporarily upon receipt of a clock signal (Φ2) at its gate to speed up the read out operation of a static random access memory.