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20 条记录 (耗时 0.014 秒)

    Terminal apparatus for resetting by remote control
    2.
    发明公开
    Terminal apparatus for resetting by remote control 失效
    通过远程控制复位的终端设备

    公开(公告)号：EP0343630A3

    公开(公告)日：1991-03-13

    申请号：EP89109387.4

    申请日：1989-05-24

    申请人： FUJITSU LIMITED

    发明人： Hiros, Ryosuke ,  Ohya, Nobumasa ,  Takizawa, Hiroshi ,  Yamana, Kenji ,  Tanikawa, Seijun ,  Yamamoto, Takahiro ,  Suzuki, Atsushi

    IPC分类号： H04L12/12

    CPC分类号： H04L12/12 ,  Y02D50/40

    摘要： A terminal apparatus having a data processing circuit (6) wherein a reset command, which is sent from another station through the same transmission line (1) and according to the same procedure as normal data sent from the station, is detected, and then the data processing circuit (6) is reset in accordance with the reset command (Fig. 3). Further, a data renewing command, which is also sent from another station through the same transmission line (1) and according to the same procedure as normal data sent from the station, is detected, and then a content of a data storage (7) in the terminal apparatus is renewed in accordance with the data renewal command.

    Data reading circuit for semiconductor memory device
    3.
    发明公开
    Data reading circuit for semiconductor memory device 失效
    数据读取电路的半导体存储器件。

    公开(公告)号：EP0235889A1

    公开(公告)日：1987-09-09

    申请号：EP87300411.3

    申请日：1987-01-19

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Atsushi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1057 ,  G11C7/062 ,  G11C7/1048 ,  G11C7/1051

    摘要： A data reading circuit for a semiconductor memory device includes: a first input terminal and a second input terminal for receiving complementary signals (DB, DB ); a first (12) and a second (11) current mirror type sense amplifiers, each of the current mirror type sense amplifiers including: a reference node (N1, N2); an output terminal; a first transistor (Q3, Q8) connected with the reference node (N1, N2); and a second transistor (Q4, Q9) connected with the output terminal. The gates of the first transistor (Q3) of a first sense amplifier (12) and of the second transistor (Q4) of a second sense amplifier (11) are connected to the first input terminal and the gates of the second transistor (Q4) of the first sense amplifier (12) and of the first transistor (Q8) of the second sense amplifier (11) are connected to the second input terminal. A first short-circuiting transistor (71) is connected between the reference nodes (N1, N2) and able to conduct temporarily upon receipt of a clock signal (Φ2) at its gate to speed up the read out operation of a static random access memory.

    Supervisory system for a primary group digital transmission line
    5.
    发明公开
    Supervisory system for a primary group digital transmission line 失效
    主要数字传输线监控系统

    公开(公告)号：EP0279452A3

    公开(公告)日：1991-01-30

    申请号：EP88102447.5

    申请日：1988-02-19

    申请人： FUJITSU LIMITED

    发明人： Nakama, Noboru ,  Motoori, Hideyuki ,  Suzuki, Atsushi ,  Sugawara, Eiji ,  Kato, Naoyuki

    IPC分类号： H04B17/02

    CPC分类号： H04B17/406

    摘要： A supervisory system for a primary group digital transmission line wherein a terminal repeater (LTE0) transmits, over a supervisory line (L), address information designating an intermediate repeater (REP0,1,2,--) and line within the intermediate repeater to be monitored while the line is in a normal, in-service condition. The terminal repeater (LTE0) and intermediate repeaters (REP0,1,2,--) are cascaded connected by way of the supervisory line (L). The terminal repeater (LTE0) and each of the intermediate repeaters (REP0,1,2,--) include amplifiers (T₁,T₂--,R₁,R₂,--) that receive and send information along the transmission line, and have a monitor output. The monitor output is processed by an error monitor (EM) within the terminal repeater (LTE0) and in each of the intermediate repeaters (REP0,1,2,--) and the results of the error monitoring provided to the supervisory line in response to polling by the terminal repeater (LTE0).

    Semiconductor memory device having function of generating write signal internally
    7.
    发明公开
    Semiconductor memory device having function of generating write signal internally 失效
    Zur internen Erzeugung eines SchreibsignalsfähigeHalbleiterspeicheranordnung。

    公开(公告)号：EP0327463A2

    公开(公告)日：1989-08-09

    申请号：EP89400302.9

    申请日：1989-02-02

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Atsushi ,  Kobayashi, Kazuya

    IPC分类号： G11C7/00

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22

    摘要： A semiconductor memory device includes : a circuit (43, 45, 46) for defining a cycle (t R , t W ) in response to a clock (CLK) and a write enable signal ( WE ) and outputting a write control signal (WS) under a specific condition; a unit (30) for inverting the clock to an inverted clock ( CLK ); a circuit (47) for generating0 a write signal (WP) in response to the inverted clock when the write control signal is output; and a memory cell array (40, 40a, 40b) in which a write access of data (D IN ) is carried out based on the write signal. A register (44) is further provided which latches the write data (D IN ) and transmits it to the memory cell array in response to the inverted clock and the write signal. An input terminal and an output terminal can be made common (T5) by making a latch timing of the write data different from that of the write enable signal, or the number of input terminals can be decreased by inputting the write data in a time sharing mode. This results in a decrease in scale of the whole circuit as a device.

    摘要翻译： 半导体存储器件包括：用于响应于时钟（CLK）和写使能信号（WE）定义周期（tR，tW）并且输出写入控制信号（WS）的电路（43,44,46） 具体条件; 用于将时钟反相到反相时钟（CLK）的单元（30）; 用于在写入控制信号被输出时响应于反相时钟产生写信号（WP）的电路（47）; 以及基于写入信号执行数据写入（DIN）的存储单元阵列（40,40a，40b）。 还提供了一个寄存器（44），其锁存写数据（DIN），并响应于反相时钟和写信号将其发送到存储单元阵列。 通过使写入数据的锁存定时与写入使能信号的锁存定时不同，输入端子和输出端子可以被公共（T5），或者可以通过在时间分配中输入写入数据来减少输入端子的数量 模式。 这导致作为器件的整个电路的规模减小。

    Supervisory system for a primary group digital transmission line
    8.
    发明公开
    Supervisory system for a primary group digital transmission line 失效
    监测系统的数字传输链路用于主基。

    公开(公告)号：EP0279452A2

    公开(公告)日：1988-08-24

    申请号：EP88102447.5

    申请日：1988-02-19

    申请人： FUJITSU LIMITED

    发明人： Nakama, Noboru ,  Motoori, Hideyuki ,  Suzuki, Atsushi ,  Sugawara, Eiji ,  Kato, Naoyuki

    IPC分类号： H04B17/02

    CPC分类号： H04B17/406

    摘要： A supervisory system for a primary group digital transmission line wherein a terminal repeater (LTE0) transmits, over a supervisory line (L), address information designating an intermediate repeater (REP0,1,2,--) and line within the intermediate repeater to be monitored while the line is in a normal, in-service condition. The terminal repeater (LTE0) and intermediate repeaters (REP0,1,2,--) are cascaded connected by way of the supervisory line (L). The terminal repeater (LTE0) and each of the intermediate repeaters (REP0,1,2,--) include amplifiers (T₁,T₂--,R₁,R₂,--) that receive and send information along the transmission line, and have a monitor output. The monitor output is processed by an error monitor (EM) within the terminal repeater (LTE0) and in each of the intermediate repeaters (REP0,1,2,--) and the results of the error monitoring provided to the supervisory line in response to polling by the terminal repeater (LTE0).

    摘要翻译： （REP0,1,2， - ）和线路的中间中继器内，以用于在主组数字传输线worin终端中继器（LTE0）发送，经一个监控线（L），地址信息在中间中继器指定监控系统 而线处于正常，在服务状态进行监视。 终端中继器（LTE0）和中间中继器（REP0,1,2， - ）被级联由监督线（L）的方式连接。 终端中继器（LTE0），并且每个中间中继器（REP0,1,2， - ）包括放大器（T1，T2 - ，R1，R2， - ）并接收和沿传输线发送的信息，和有 显示器输出。 显示器输出由误差监视器（EM）的终端中继器内（LTE0）上，并在每一个中间中继器的处理（REP0,1,2， - ）和错误监视的结果在响应提供给监控线 要由终端中继器（LTE0）轮询。

    Semiconductor memory device
    9.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0239021A2

    公开(公告)日：1987-09-30

    申请号：EP87104103.4

    申请日：1987-03-20

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Atsushi ,  Itoh, Hideo

    IPC分类号： G11C7/00 ,  G11C11/41

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C11/419

    摘要： A semiconductor memory device is provided with a clamp circuit (13) for clamping a driving level of a write circuit (12) so that the information on a bit line (BL i , BI i ; i = 1,2...n) can be transmitted quickly to a data bus (DB, DB ) at the time of a read-out operation by using transistors having a low threshold value (or a large mutual conductance) for the transistors (T1, T2) constituting a column transfer gate, and so that a write-in operation can be carried out at a high speed by using transistors having a large mutual conductance for driving transistors (T3, T4) of the write circuit (12) and setting a required level by clamping the driving level of the write circuit (12).

    摘要翻译： 一种半导体存储器件设置有钳位电路（13），用于钳位写入电路（12）的驱动电平，使得关于位线（BLi，BI i; i = 1,2 ... n）的信息可以 通过对构成列传输门的晶体管（T1，T2）使用具有低阈值（或大互导）的晶体管，在读出操作时被快速传输到数据总线（DB，DB） 并且通过使用具有大互导性的晶体管来驱动写入电路（12）的晶体管（T3，T4）并且通过将驱动电平钳位到所需的电平来设置所需电平，从而可以高速执行写入操作 写入电路（12）。