发明公开
- 专利标题： Buffer circuit for integrated circuit
- 专利标题（中）： 缓冲电路的集成电路。
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申请号： EP87300143.2申请日： 1987-01-08
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公开(公告)号： EP0237139A1公开(公告)日： 1987-09-16
- 发明人: Toda, Haruki , Miyawaki, Naokazu , Koinuma, Hiroyuki
- 申请人： KABUSHIKI KAISHA TOSHIBA
- 申请人地址： 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址： 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 代理机构： Freed, Arthur Woolf
- 优先权： JP1609/86 19860108
- 主分类号： H03K19/094
- IPC分类号： H03K19/094 ; H03K19/003 ; H03K5/02
摘要：
n the buffer circuit (B) for an integrated circuit according to this invention a load MOS transistor (Q1) and a drive MOS transistor (Q2) are connected in series between a power source potential node (Vcc') and a ground potential node (Vss') of the integrated circuit. A constant current circuit means (Q3) is connected in series with a circuit including the load MOS transistor (Q1) and the drive MOS transistor (Q2).
公开/授权文献
- EP0237139B1 Buffer circuit for integrated circuit 公开/授权日：1991-06-19
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