A vertical deflection amplifier (20) of a video display apparatus includes first (Q1) and second (Q2) transistor amplifier output stages arranged in a totem-pole, push-pull configuration. A vertical deflection winding (Lv) is coupled to the output stages at a deflection amplifier output terminal (22). An S-capacitor (C1) is coupled to the deflection winding (L v ) at a second terminal (21) remote from the output terminal (22). A source (23) of deflection rate signals is coupled to the deflection amplifier (20) for generating a deflection current (iv) in the deflection winding (Lv). A base current generating circuit (40) is coupled to one (Q1) of the transistor amplifier output stages for providing base current (i 1) thereto. The S-capacitor voltage (V1) is applied to the base current generating circuit (40) for enabling conduction of base current (i1) in the one amplifier output stage (Q1). When the video display apparatus is first turned on, the initially discharged S-capacitor (C1) is slowly charged from a DC voltage supply (+30V) to delay generation of vertical deflection past completion of picture tube degaussing.