A memory system includes a data storage matrix (11) having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses (B0-B7) each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a se­quence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defec­tive physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix (31). Redundancy control logic (25, 30, 32, 33, 34) response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the re­dundant column between the data bits read from the data storage matrix according to its logical column address.