发明公开
EP0247324A3 Improved random access memory employing complementary transistor switch (CTS) memory cells
失效
改进的随机访问存储器使用补充晶体管开关(CTS)存储器单元
- 专利标题: Improved random access memory employing complementary transistor switch (CTS) memory cells
- 专利标题(中): 改进的随机访问存储器使用补充晶体管开关(CTS)存储器单元
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申请号: EP87104578.7申请日: 1987-03-27
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公开(公告)号: EP0247324A3公开(公告)日: 1990-10-10
- 发明人: Chan, Yuen Hung , Struk, James Robert
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Schuffenecker, Thierry
- 优先权: US857903 19860430
- 主分类号: G11C11/411
- IPC分类号: G11C11/411 ; G11C11/416 ; G11C11/417
摘要:
Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.
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