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公开(公告)号：EP0168633A2
公开(公告)日：1986-01-22
申请号：EP85107230.6
申请日：1985-06-13
IPC分类号： G11C11/415 , G11C11/416
CPC分类号： G11C11/416 , G11C11/415
摘要： The disclosure is directed to an improved random access memory (RAM). More particularly, to improved selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.
The word selection part of the circuitry uses a voltage mode selection scheme; the bit select part has a circuitry for discharging stored charges on the bit lines and a circuit for up level clamping the bit line for limiting the upper potential level.-
公开(公告)号：EP0328841B1
公开(公告)日：1993-10-13
申请号：EP88480089.7
申请日：1988-12-06
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公开(公告)号：EP0168633B1
公开(公告)日：1992-01-29
申请号：EP85107230.6
申请日：1985-06-13
IPC分类号： G11C11/415 , G11C11/416
CPC分类号： G11C11/416 , G11C11/415
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4.发明公开Improved random access memory employing complementary transistor switch (CTS) memory cells 失效改进的随机访问存储器使用补充晶体管开关（CTS）存储器单元
公开(公告)号：EP0247324A3
公开(公告)日：1990-10-10
申请号：EP87104578.7
申请日：1987-03-27
IPC分类号： G11C11/411 , G11C11/416 , G11C11/417
CPC分类号： G11C11/416 , G11C11/4113 , G11C11/417
摘要： Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.
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公开(公告)号：EP0328841A3
公开(公告)日：1990-12-05
申请号：EP88480089.7
申请日：1988-12-06
摘要： An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
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公开(公告)号：EP0168633A3
公开(公告)日：1989-02-01
申请号：EP85107230.6
申请日：1985-06-13
IPC分类号： G11C11/415 , G11C11/416
CPC分类号： G11C11/416 , G11C11/415
摘要： The disclosure is directed to an improved random access memory (RAM). More particularly, to improved selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells. The word selection part of the circuitry uses a voltage mode selection scheme; the bit select part has a circuitry for discharging stored charges on the bit lines and a circuit for up level clamping the bit line for limiting the upper potential level.
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7.发明授权Improved random access memory employing complementary transistor switch (CTS) memory cells 失效改进的随机访问存储器使用补充晶体管开关（CTS）存储器单元
公开(公告)号：EP0247324B1
公开(公告)日：1993-08-18
申请号：EP87104578.7
申请日：1987-03-27
IPC分类号： G11C11/411 , G11C11/416 , G11C11/417
CPC分类号： G11C11/416 , G11C11/4113 , G11C11/417
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8.发明公开Asymmetrical delay generator for a clock chopper 失效不对称的Verzögerungsgeneratorfüreinen Taktzerhacker。
公开(公告)号：EP0328841A2
公开(公告)日：1989-08-23
申请号：EP88480089.7
申请日：1988-12-06
摘要： An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
摘要翻译： 公开了一种用于时钟斩波电路的不对称延迟发生器。 该电路中有一个互补的晶体管开关存储单元。 该单元以这样的模式操作，其中单元的一半在饱和模式下工作。 电池的一半控制斩波器的脉冲宽度。 电池的另一半不工作在饱和状态，并控制斩波器的复位，从而控制电路工作的最大时钟速率。
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9.发明公开Improved random access memory employing complementary transistor switch (CTS) memory cells 失效RAM-Speicher mitKomplementärystistor-Schalterspeicherzellen。
公开(公告)号：EP0247324A2
公开(公告)日：1987-12-02
申请号：EP87104578.7
申请日：1987-03-27
IPC分类号： G11C11/411 , G11C11/416 , G11C11/417
CPC分类号： G11C11/416 , G11C11/4113 , G11C11/417
摘要： Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.
摘要翻译： 公开了用于RAM的改进的位选择电路，特别是采用CTS（互补晶体管开关）单元的位选择电路。 位选择电路包括互连的第一和第二级矩阵解码器，每个存储器列具有一对位线，每对位线连接到位选择电路装置，每个所述位选择电路装置连接到所述 第二电平解码器，连接到每对位线的每个所述位选择电路装置的位上电平钳位电路，每个所述位选择电路装置包括第一电路装置，用于增加所选择的一对位的选择速度 所述位上电平钳位电路与所述选择的一对位线的所述位选择电路装置协作，用于积极地限制所述选择的位线对的上电位电平，并且每个所述位选择电路装置包括第二电路装置 用于增加所选择的一对位线的取消选择速度。
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