Timing unit for generating a timing signal for synchronous microprocessors (such as microprocessor 68020) in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor, a frequency divider divides the base frequency by four and provides such timing frequency, and a shift register clocked by the base frequency and receiving in input a timing signal in output from the frequency divider, generates a mask signal,which is selectively applied to a control input of the frequency divider, depending on presence of one or more control signals, to inhibit the switching of the frequency divider thereby introducing in the phases of the timing frequency wait states equal to 1/4 (or mutliple thereof) of the timing frequency.