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公开(公告)号：EP0691704B1
公开(公告)日：1999-11-03
申请号：EP94830339.1
申请日：1994-07-07
发明人： Spagna, Danilo
IPC分类号： H01R23/66 , H01R13/631 , H05K7/14
CPC分类号： H01R12/79 , H01R13/6315 , H05K7/1454
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2.发明公开Memory control unit with programmable timing 失效Speichersteinungeninititheit mit programmierbaren Zeitsignalen
公开(公告)号：EP0926599A1
公开(公告)日：1999-06-30
申请号：EP97830718.9
申请日：1997-12-24
CPC分类号： G06F13/1689 , G06F13/1694 , G11C29/32
摘要： Control unit (Cm) for a central memory (115) of a computer system capable of generating sequences of commands for the said memory (115), each sequence comprising a plurality of commands separated from each other according to a timing defined by periods of a clock signal, in which the control unit (Cm) includes means (230, 233) for programming the timings of the command sequences in the control unit (Cm) installed in the computer system (100).
摘要翻译： 用于能够产生所述存储器（115）的命令序列的计算机系统的中央存储器（115）的控制单元（Cm），每个序列包括根据由所述存储器（115）的周期定义的定时彼此分离的多个命令 时钟信号，其中控制单元（Cm）包括用于对安装在计算机系统（100）中的控制单元（Cm）中的命令序列的定时进行编程的装置（230,233）。
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3.发明公开Method for reading data from a shared memory in a multiprocessor computer system 失效一种用于在多处理器计算机系统读取上的共享存储器中的数据的方法
公开(公告)号：EP0923031A1
公开(公告)日：1999-06-16
申请号：EP97830657.9
申请日：1997-12-11
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0884
摘要： Method (T1-T13) for reading data in a computer system comprising a plurality of processors and a shared memory, at least one of the processors having a cache memory for storing corresponding data of the shared memory, the method comprising the steps of requesting (T1-T3) the reading of a data element from the shared memory by a requesting processor, reading (T4-T13) the requested data element from the shared memory and, in parallel, checking whether the requested data element is present in modified form in the cache memory of each processor other than the requesting processor, interrupting (T13) the reading of the requested data element from the shared memory if it is not ascertained (T11) that the requested data element is not present in modified form in the cache memory of any processor other than the requesting processor.
摘要翻译： 方法（T1-T13），用于在一个计算机系统，包括处理器的多元性和共享存储器，具有用于存储所述共享存储器的相应数据的高速缓存存储器中的处理器中的至少一个读取数据，该方法包括：请求步骤（ T1-T3）从共享存储器中的数据元素的由请求处理器，读（T4-T13）从共享存储器，并同步所请求的数据元素，检查是否所请求的数据元素存在于在修饰体中的读 如果它没有确定（T11）比发出请求的处理器，中断（T13）从共享存储器的请求的数据元素的读取之外的每个处理器的高速缓冲存储器那样所请求的数据元素不存在修饰形式在高速缓冲存储器 比请求的处理器之外的任何处理器。
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4.发明公开Interface bridge between a system bus and local buses with translation of local addresses for system space access programmable by address space 失效系统总线和局部总线与本地地址转换为可编程之间Busschnittstellebrücke意味着地址空间系统空间访问
公开(公告)号：EP0887738A1
公开(公告)日：1998-12-30
申请号：EP97830308.9
申请日：1997-06-27
发明人： Casamata, Angelo
CPC分类号： G06F13/404
摘要： Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.
摘要翻译： 一个系统总线（ASBUS）和至少一个本地总线（11，12）之间的接口桥（13），该系统的空间直接通过所述的系统总线寻址比所述系统的空间更大通过本地总线直接寻址，包括一个多元化 可编程的解码器（17，18，19）其中的每一个定义的范围内的不同范围通过本地总线直接寻址，以及一系列属性作为局部总线的地址范围被翻译或直接传输到系统总线，并且因此 标识一个本地总线地址为包括或以其他方式的范围内，所以也取决于是否在局部总线地址属于范围中的一个或不与上所述范围属性，局部总线地址被传输到系统总线作为直接 地址或作为解决由一个转换逻辑（20，21）以及能够寻址整个系统空间的转换。
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公开(公告)号：EP0777182A1
公开(公告)日：1997-06-04
申请号：EP95830495.8
申请日：1995-11-28
发明人： Zulian, Ferruccio
CPC分类号： G11C11/4074 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A memory access limiter for random access dynamic memory of data processing systems formed by several modules (MM1, ... MMN) which can be independently activated in partial temporal superimposition, each by a memory start command (START.M), comprising a bidirectional counter (3, 15) which periodically increments at a constant period defined by a clock signal (CLK), by a value representative of the electrical charge delivered by a power supply (1) to an output buffer capacitor (2) and decrements, at each memory start command, by a value representative of the electrical charge drained at each memory operation activated by the memory start command, a predetermined decremented count state of the counter identifying a maximum admissible discharge condition of the buffer capacitor below which it is necessary to inhibit any further activation of the memory until the count state of the counter is no longer below the predetermined count state.
摘要翻译： 一种用于数据处理系统的随机存取动态存储器的存储器访问限制器，所述数据处理系统由多个模块（MM1，...，MMN）形成，所述模块可以在部分时间叠加中独立地激活，每个模块由存储器启动命令（START.M） 计数器（3,15），其以由时钟信号（CLK）限定的恒定周期周期性地增加表示由电源（1）传送到输出缓冲电容器（2）的电荷的值，并且在 每个存储器启动命令通过代表在由存储器启动命令激活的每个存储器操作时排出的电荷的值，计数器的预定减量计数状态识别缓冲电容器的最大允许放电条件，在该最大允许放电条件下，必须抑制 存储器的任何进一步激活，直到计数器的计数状态不再低于预定的计数状态。
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6.发明公开A releasable mount heat-sink for a very large scale integrated circuit 失效Lösbar更新WärmesenkefürVLSI-Schaltung
公开(公告)号：EP0750341A1
公开(公告)日：1996-12-27
申请号：EP95830252.3
申请日：1995-06-19
发明人： Spagna, Danilo
IPC分类号： H01L23/00 , H01L23/467 , H01L23/40
CPC分类号： H01L23/4006 , H01L23/467 , H01L2023/4062 , H01L2023/4081 , H01L2924/0002 , H01L2924/00
摘要： A highly efficient releasable mount heat-sink for a very large scale integrated circuit comprises a single piece (1) of a high thermal conductivity material formed of two mutually parallel plates (3,4) interconnected by a plurality of fins (2) lying across said plates to form a plurality of ducts for a refrigerating gas flow, the piece being formed with a plurality of housings (5,6,7,8) for means (16,17,18,19,20,21) of securing the heat-sink on a support (15) of the integrated circuit (14) with one (3) of the plates in contact with the integrated circuit (14).
摘要翻译： 用于非常大规模的集成电路的高效率的可拆卸安装的散热器包括由两个相互平行的板（3,4）形成的高导热材料的单件（1），所述两个相互平行的板（3,4）由跨过多个翅片 所述板形成用于制冷气体流的多个管道，所述管件形成有多个用于固定所述壳体（5,6,7,8）的装置（5,6,7,8） 在集成电路（14）的支撑件（15）上散热，其中一个（3）的板与集成电路（14）接触。
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7.发明公开Annotation data processing system with hypermedia processable and active annotations 失效Anmerkungsverarbeitungsanlage mit hypermediaverarbeitbaren und aktiven Anmerkungen。
公开(公告)号：EP0650126A1
公开(公告)日：1995-04-26
申请号：EP93830424.3
申请日：1993-10-21
发明人： Albini, Alessandro , Cicu, Antonio , Scamuzzo, Stefano , Toppeta, Donato , Popescu Janu, Michele
IPC分类号： G06F17/00
CPC分类号： G06F17/30014 , G06F17/241
摘要： Electronic system architecture for electronic document annotation by hypermedia processable and active annotations, comprising a data processing system, (4,5,6,7,8,9) having at least a user terminal (1,2,3) an operating system (16) for information managing according to a plurality of structural models, navigation means (13,14,15) for navigation from anchors in an information structure, documents in particular, editing means (11,12) activated from terminal for getting access to the documents through the navigation means (13,14,15) and annotation means (17,18,19,20) coupled to the navigation means (13), to the terminal (1,2,3) and to the operating system (16) for creating and processing annotations comprising contents, treated as a linkable node (23) of the information structure and a set of entities-relations, structured in accordance to an entity-relation model, the set being connected to the node, so that each annotation is retrievable through the navigation means (13,14,15) and is further retrievable and processable by the annotation means (17,18,19) according to relational criteria and, based on events, identified as entities of the annotation structured set, automatically starts processes such as note deletion or notification to an addressee.
摘要翻译： 包括具有至少一用户终端（1,2,3）操作系统（4,5,6,7,8,9）的数据处理系统（4,5,6,7,8,9）的通过超媒体可处理和主动注释的电子文档注释的电子系统架构 16），用于根据多个结构模型的信息管理，用于从信息结构中的锚导航的导航装置（13,14,15），特别是文档，从终端激活以访问 通过与导航装置（13）耦合的导航装置（13,14,15）和注释装置（17,18,19,20）到终端（1,2,3）和操作系统（16） ），用于创建和处理包括内容的注释，被视为信息结构的可链接节点（23），以及一组根据实体关系模型构造的实体关系，所述集合连接到节点，使得每个 注释可以通过导航装置（13,14,15）检索，并且是fu 通过注释手段（17,18,19）可以根据关系标准进行检索和处理，并且基于被标识为注释结构化集合的实体的事件，自动地开始诸如注释删除或通知给收件人的处理。
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公开(公告)号：EP0307793B1
公开(公告)日：1995-04-05
申请号：EP88114666.6
申请日：1988-09-08
发明人： Rendina, Francesco , Savogin, Lucio
CPC分类号： H04L25/028 , G06F13/4072 , H04L25/0292
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公开(公告)号：EP0401588B1
公开(公告)日：1995-02-15
申请号：EP90109654.5
申请日：1990-05-21
发明人： Boioli, Roberto , Munero, Carlo , Savogin, Lucio
CPC分类号： G06F13/4027 , G06F13/409
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10.发明公开Variable interleaving level memory and related configuration unit 失效Speicher mit variabelerVerschachtelungshöheund verwandte Konfigurationseinheit。
公开(公告)号：EP0629952A1
公开(公告)日：1994-12-21
申请号：EP93830263.5
申请日：1993-06-16
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： A variable interleaving level memory wherein a plurality of independently addressable storage modules are present in a number between 1 and a maximum, comprising a circuit means (14) which, according to the number of the modules present and their capacity, responds to a first field of least-weight address bits (ALOW) and a second field of greater-weight address bits (AHIGH) input thereto by generating a module selection signal for selecting from the various modules present and a plurality of signals (MBIT) representing module address bits, thereby configuring the memory with the highest levels of interleaving and for maximum storage capacity, as allowed for by the number and capacity of the modules present and properly addressing each time the selected module.
摘要翻译： 一种可变交错级存储器，其中多个可独立寻址的存储模块以1和最大值之间的数量存在，包括电路装置（14），其根据存在的模块的数量及其容量对第一场 通过生成用于从存在的各种模块中选择的模块选择信号和表示模块地址位的多个信号（MBIT）的最小权重地址位（ALOW）和其中输入的较大权重地址位（AHIGH）的第二字段， 从而配置具有最高级别的交织和最大存储容量的存储器，如存在的模块的数量和容量所允许的，并且在每次所选择的模块时适当地寻址。
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