A digital data processor acts on a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. The operation code field of the branch and return on address instruction is into an instruction register, the memory exit address field of the loaded branch and return on address instruction is loaded into the address register and the memory entry address field of the branch and return on address instruction is loaded into the program counter. The next sequential address following the address of the current BAROA instruction is then stored in a register stack, and a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction is fetched and executed. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. The memory address in the program counter is compared with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.