公开(公告)号：EP0609626A2

公开(公告)日：1994-08-10

申请号：EP93310452.3

申请日：1993-12-23

申请人： International Business Machines Corporation

发明人： Salcedo, Louis ,  Cazzolla, John Joseph ,  Crouse, Richard Stephen ,  Chang, Luke Lung ,  Hurtado, Marco Montalvo ,  Nguyen, Kha Dinh ,  Rivero, Jose Luis ,  Ruiz, Jose Joaquin

IPC分类号： H04L12/50 ,  H04Q3/00 ,  H04Q11/04

CPC分类号： H04L49/351 ,  H04L49/101 ,  H04L49/3018 ,  H04L49/3027 ,  H04L2012/445

摘要： A serial simplex switch 14 design is provided which includes I/O ports 20 each of which is configurable specifically for attachment to a data communications subsystem 12 or, alternatively, for cascaded connection to a similarly configured I/O port 20 on another switch 14. The switch 14 provides a packet routing function including input 32 and output 36 buffers for each of its I/O ports 20 wherein packets of control messages sent by one subsystem 20 are temporarily stored prior to being delivered to the appropriate destination subsystem 20. When configured to be directly attached to a subsystem 20, the I/O ports 20 separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port 20. Each I/O port 20 is configurable to either of these methods of operation by means of programmable latches associated with the I/O port 20.

摘要翻译： 级联单工交换机具有简单的串行交叉开关，其包括几个I / O端口，每个I / O端口适于连接到通信子系统，该通信子系统将数据和控制消息传递到其他通信子系统或者在其上的几个第二I / O端口之一 第二单纯串联交叉开关。 每个第一个I / O端口都有可编程锁存器，用于对其进行编程。 如果端口连接到通信子系统，则单个第一端口连接到单个子系统，并且管理发送到子系统和从子系统发送的数据和控制消息。 如果级联，则该对第一I / O端口之一管理数据传输，另一对管理消息的传送。

公开(公告)号：EP0263447A3

公开(公告)日：1990-04-25

申请号：EP87114429.1

申请日：1987-10-02

申请人： International Business Machines Corporation

发明人： Crouse, Richard Stephen ,  Boudreaux, Randall Paul ,  Cazzolla, John Joseph, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/30054 ,  G06F8/66 ,  G06F9/322 ,  G06F9/328 ,  G06F9/4486

摘要： A digital data processor acts on a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. The operation code field of the branch and return on address instruction is into an instruction register, the memory exit address field of the loaded branch and return on address instruction is loaded into the address register and the memory entry address field of the branch and return on address instruction is loaded into the program counter. The next sequential address following the address of the current BAROA instruction is then stored in a register stack, and a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction is fetched and executed. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. The memory address in the program counter is compared with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.

公开(公告)号：EP0609626A3

公开(公告)日：1995-04-05

申请号：EP93310452.3

申请日：1993-12-23

申请人： International Business Machines Corporation

发明人： Salcedo, Louis ,  Cazzolla, John Joseph ,  Crouse, Richard Stephen ,  Chang, Luke Lung ,  Hurtado, Marco Montalvo ,  Nguyen, Kha Dinh ,  Rivero, Jose Luis ,  Ruiz, Jose Joaquin

IPC分类号： H04L12/50 ,  H04Q3/00 ,  H04Q11/04

CPC分类号： H04L49/351 ,  H04L49/101 ,  H04L49/3018 ,  H04L49/3027 ,  H04L2012/445

摘要： A serial simplex switch 14 design is provided which includes I/O ports 20 each of which is configurable specifically for attachment to a data communications subsystem 12 or, alternatively, for cascaded connection to a similarly configured I/O port 20 on another switch 14. The switch 14 provides a packet routing function including input 32 and output 36 buffers for each of its I/O ports 20 wherein packets of control messages sent by one subsystem 20 are temporarily stored prior to being delivered to the appropriate destination subsystem 20. When configured to be directly attached to a subsystem 20, the I/O ports 20 separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port 20. Each I/O port 20 is configurable to either of these methods of operation by means of programmable latches associated with the I/O port 20.

公开(公告)号：EP0263447A2

公开(公告)日：1988-04-13

申请号：EP87114429.1

申请日：1987-10-02

申请人： International Business Machines Corporation

发明人： Crouse, Richard Stephen ,  Boudreaux, Randall Paul ,  Cazzolla, John Joseph, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/30054 ,  G06F8/66 ,  G06F9/322 ,  G06F9/328 ,  G06F9/4486

摘要： A digital data processor acts on a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. The operation code field of the branch and return on address instruction is into an instruction register, the memory exit address field of the loaded branch and return on address instruction is loaded into the address register and the memory entry address field of the branch and return on address instruction is loaded into the program counter. The next sequential address following the address of the current BAROA instruction is then stored in a register stack, and a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction is fetched and executed. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. The memory address in the program counter is compared with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.

摘要翻译： 一种数字数据处理器作用于分支而在地址返回到具有操作码字段，一个存储器地址输入字段和一个存储器地址字段出口（Baroa）指令。 分支机构的操作码字段和返回上的地址指令是进入到指令寄存器，加载分支的内存退出地址栏和地址返回指令被加载到地址寄存器和分支的内存入口地址字段和回报 地址指令被装入程序计数器。 然后下一个顺序地址继当前Baroa指令的地址被存储在寄存器堆，并且与驻留在由分支而在地址指令返回所提供的存储器条目地址的指令开始的指令序列被取出并执行。 程序计数器递增上指令每次被执行。 以这种方式，程序计数器提供的指令的存储器地址取出。 在程序计数器的存储器地址与地址寄存器中的出口地址和装载返回指令操作码到指令寄存器当程序计数器的存储器地址变为等于地址寄存器中的出口地址相比，寻求返回指令 操作码，反过来，使存储在寄存器堆栈的地址被加载到程序计数器中。