发明公开
EP0270219A2 Reduced parallel EXCLUSIVE OR and EXCLUSIVE NOR gate
失效
Paralleles EXKLUSIV-OR- und EXKLUSIV-NOR-Gatter mit reduziertem Schaltaufwand。
- 专利标题： Reduced parallel EXCLUSIVE OR and EXCLUSIVE NOR gate
- 专利标题（中）： Paralleles EXKLUSIV-OR- und EXKLUSIV-NOR-Gatter mit reduziertem Schaltaufwand。
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申请号： EP87308916.3申请日： 1987-10-08
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公开(公告)号： EP0270219A2公开(公告)日： 1988-06-08
- 发明人: Khosrow, Hedayati
- 申请人： INTERSIL, INC. (a Delaware corp.)
- 申请人地址： 2450 Walsh Avenue Santa Clara California 95051 US
- 专利权人： INTERSIL, INC. (a Delaware corp.)
- 当前专利权人： INTERSIL, INC. (a Delaware corp.)
- 当前专利权人地址： 2450 Walsh Avenue Santa Clara California 95051 US
- 代理机构： Kennington, Eric Alasdair
- 优先权： US916869 19861009
- 主分类号： H03K19/21
- IPC分类号： H03K19/21 ; G06F7/50
摘要：
A parallel EXCLUSIVE OR and EXCLUSIVE NOR gate comprises four groups of three transistors. In each group of transistors, one (60,62,66,70) is part of the EXCLUSIVE NOR gate only, one (74,76,78,80) is part of the EXCLUSIVE OR gate only, and one (56,58,64,68) is a part of both gates. The gates may be constructed in a manner similar to a known circuit using tri-inverters, but since one transistor in every group of three has a dual membership of both gates, the total circuit requires 12 transistors instead of 16.
公开/授权文献
- EP0270219A3 Reduced parallel EXCLUSIVE OR and EXCLUSIVE NOR gate 公开/授权日：1989-05-10
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