公开(公告)号：EP0238646B1

公开(公告)日：1990-12-05

申请号：EP86906203.4

申请日：1986-10-07

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： THURBER, Charles, Raymond, Jr.

IPC分类号： H03M1/52

CPC分类号： H03M1/52

摘要： Conversion is achieved by subdividing the intergrate and deintegrate periods into a plurality of integrate and deintegrate phases. Power frequency rejection can be maintained by defining the combined integrate phases to integrate over at least one complete power line cycle. Sychronization of the integrate phases with the power line cycle is maintained by separating integrate phases with a combined deintegrate and rest phase of fixed duration.

公开(公告)号：EP0260515A3

公开(公告)日：1990-09-26

申请号：EP87112663.7

申请日：1987-08-31

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Wei, James Yuan ,  Hedayati, Khosrow

IPC分类号： G06F7/52 ,  G06F7/50

CPC分类号： G06F7/533 ,  G06F7/509

摘要： The invention performs the multiplication and/or accumulation of digital numbers in either two's complement or unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.

公开(公告)号：EP0265554A1

公开(公告)日：1988-05-04

申请号：EP86115146.2

申请日：1986-10-31

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Wei, James Yuan

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G11C16/0433 ,  H03K19/17712

摘要： Disclosed is a programmable logic gate array employing a plurality of reprogrammable fuses (20) having a logical NAND characteristic for logically connecting selected inputs (A o -A n ) to selected logic gates (22). Means E 5 , P s are also disclosed for programming said fuses and for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.

摘要翻译： 公开了一种可编程逻辑门阵列，其采用具有逻辑NAND特性的多个可重新编程熔丝（20），用于将所选输入（A o-A n）逻辑连接到所选逻辑门（22）。 还公开了装置E5，Ps，用于对所述保险丝进行编程，并提供适当的信号以允许逻辑门阵列的三种操作模式; 编程，擦除和正常逻辑运算。

公开(公告)号：EP0254992A2

公开(公告)日：1988-02-03

申请号：EP87110354.5

申请日：1987-07-17

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Mostyn, Graham Yorke ,  Yunus, Mohammad

IPC分类号： H02H3/24

CPC分类号： H02H3/24

摘要： The duration of time during which an AC power vottage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform In the region of zero voltage crossing, the expected time duration between voltage thresholds is approximately 6% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

摘要翻译： AC电源电压正弦波形保持在负电压阈值-V1伏特，标称值为负峰值电压-V2伏特的5％和正电压阈值+ V1伏之间的持续时间，标称值为峰值正电压+ V2伏特的5％ ，被检测到。 通过在零电压交叉区域中由正弦波形显示的电压随时间的变化，电压阈值之间的预期持续时间约为这种正弦波形的一半周期的5％。 如果电压阈值之间的实际时间超过（标称）为该值的两倍或者半个周期的10％，则检测掉电状态，并产生电源故障信号。

公开(公告)号：EP0260515A2

公开(公告)日：1988-03-23

申请号：EP87112663.7

申请日：1987-08-31

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Wei, James Yuan ,  Hedayati, Khosrow

IPC分类号： G06F7/52 ,  G06F7/50

CPC分类号： G06F7/533 ,  G06F7/509

摘要： The invention performs the multiplication and/or accumulation of digital numbers in either two's complement or unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.

摘要翻译： 本发明执行二进制补码或无符号幅值表示中的数字数字的乘法和/或累加。 修改后的Booth算法将产生的部分产品数量最小化。 两个加法器阵列并行地求和部分乘积以产生中间值，然后由第三加法器阵列求和。 部分产品以优化电路速度的方式在两个加法器阵列之间分配。

公开(公告)号：EP0260515B1

公开(公告)日：1994-02-23

申请号：EP87112663.7

申请日：1987-08-31

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Wei, James Yuan ,  Hedayati, Khosrow

IPC分类号： G06F7/52 ,  G06F7/50

CPC分类号： G06F7/533 ,  G06F7/509

公开(公告)号：EP0254992A3

公开(公告)日：1989-10-18

申请号：EP87110354.5

申请日：1987-07-17

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Mostyn, Graham Yorke ,  Yunus, Mohammad

IPC分类号： H02H3/24

CPC分类号： H02H3/24

摘要： The duration of time during which an AC power vottage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform In the region of zero voltage crossing, the expected time duration between voltage thresholds is approximately 6% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

公开(公告)号：EP0270219A3

公开(公告)日：1989-05-10

申请号：EP87308916.3

申请日：1987-10-08

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Khosrow, Hedayati

IPC分类号： H03K19/21 ,  G06F7/50

CPC分类号： G06F7/501 ,  H03K19/215

摘要： A parallel EXCLUSIVE OR and EXCLUSIVE NOR gate comprises four groups of three transistors. In each group of transistors, one (60,62,66,70) is part of the EXCLUSIVE NOR gate only, one (74,76,78,80) is part of the EXCLUSIVE OR gate only, and one (56,58,64,68) is a part of both gates. The gates may be constructed in a manner similar to a known circuit using tri-inverters, but since one transistor in every group of three has a dual membership of both gates, the total circuit requires 12 transistors instead of 16.

公开(公告)号：EP0270219A2

公开(公告)日：1988-06-08

申请号：EP87308916.3

申请日：1987-10-08

申请人： INTERSIL, INC. (a Delaware corp.)

发明人： Khosrow, Hedayati

IPC分类号： H03K19/21 ,  G06F7/50

CPC分类号： G06F7/501 ,  H03K19/215

摘要： A parallel EXCLUSIVE OR and EXCLUSIVE NOR gate comprises four groups of three transistors. In each group of transistors, one (60,62,66,70) is part of the EXCLUSIVE NOR gate only, one (74,76,78,80) is part of the EXCLUSIVE OR gate only, and one (56,58,64,68) is a part of both gates. The gates may be constructed in a manner similar to a known circuit using tri-inverters, but since one transistor in every group of three has a dual membership of both gates, the total circuit requires 12 transistors instead of 16.

摘要翻译： 并行的EXCLUSIVE OR或EXCLUSIVE或非门包括四组三个晶体管。 在每组晶体管中，一个（60,626,670）只是独占或非门的一部分，一个（74,76,78,80）是唯一或门的一部分，一个（56,58 ，64,68）是两门的一部分。 门可以以类似于使用三逆变器的已知电路的方式构造，但是由于三组中的每一组中的一个晶体管具有两个门的双重成员，所以总电路需要12个晶体管而不是16个晶体管。