A computer system architecture implementing multiple central processing units, each including a split instruc­tion and operand cache, and that provides for the manage­ment of multiple copies (line pairs) of a memory line through the use of a line pair state is described. System­atic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture imple­ments the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the in­struction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depend­ing on whether the operand buffer destination is a memory line that is a member of a line pair.