公开(公告)号：EP0271187A2

公开(公告)日：1988-06-15

申请号：EP87308811.6

申请日：1987-10-05

申请人： AMDAHL CORPORATION

发明人： Woffinden, Gary A. ,  Ertl, Robert A. ,  Thomas, Jeffrey A. ,  Robinson, Theodore S. ,  Millar, James P. ,  Finan, Christopher D. ,  Petolino, Joseph A., Jr. ,  Shah, Ajay K. ,  Wang, Shen H. ,  Semmelmeyer Mark W.

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

摘要： A computer system architecture implementing multiple central processing units, each including a split instruc­tion and operand cache, and that provides for the manage­ment of multiple copies (line pairs) of a memory line through the use of a line pair state is described. System­atic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture imple­ments the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the in­struction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depend­ing on whether the operand buffer destination is a memory line that is a member of a line pair.

摘要翻译： 描述了实现多个中央处理单元的计算机系统架构，每个中央处理单元包括分割指令和操作数高速缓存，并且通过使用线对状态来管理存储器线的多个副本（线对）。 当指令和操作数据高速缓存存储器传输时，存储器线路的系统管理允许系统的完整性始终保持。 分离高速缓存架构管理确定具有第一预定系统地址的存储器线是否存在于指令和操作数高速缓存存储器中，或者将在存储器线路上移动。 维持地址标签线对状态信息以允许确定各个存储器线对成员是否存在和在何处驻留。 该架构在将存储器线路的每次传送到系统的任何分割高速缓存时实现对线路的管理。 只要在单个中央处理器的每个指令和操作数缓存缓冲器中的相同相对位置存在相同的存储器线，就允许线对存在。 该架构还包括数据路径选择器，用于根据操作数缓冲目标是作为线对的成员的存储线，将操作数数据传送到指令或操作数数据高速缓冲存储器或两者。

公开(公告)号：EP0260862A2

公开(公告)日：1988-03-23

申请号：EP87307922.2

申请日：1987-09-08

申请人： AMDAHL CORPORATION

发明人： Thomas, Jeffrey A. ,  Robinson, Theodore S. ,  Ertl, Robert A. ,  Christense, Harold F. Jr.,

IPC分类号： G06F12/08

CPC分类号： G06F5/06 ,  G06F12/0804

摘要： A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit is described. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.

摘要翻译： 描述了用于在中央处理器单元的高速缓冲存储器和主存储器单元之间的受控缓冲和传送数据的队列缓冲器。 本发明的队列缓冲器优选地包括用于数据的排队存储的缓冲存储器和用于引导从高速缓冲存储器直接接收的数据的名义上即时接受和存储的控制器，以及用于来自队列缓冲器的数据的标称系统后台传送 到主机存储单元。 相对于队列缓冲存储器的存储器传输的这种标称优先级允许需要来自主存储单元的数据的数据移入请求继续进行，同时所需的移出数据从高速缓冲存储器立即移动到缓冲器队列存储器。

公开(公告)号：EP0271187B1

公开(公告)日：1995-12-20

申请号：EP87308811.6

申请日：1987-10-05

申请人： AMDAHL CORPORATION

发明人： Woffinden, Gary A. ,  Ertl, Robert A. ,  Thomas, Jeffrey A. ,  Robinson, Theodore S. ,  Millar, James P. ,  Finan, Christopher D. ,  Petolino, Joseph A., Jr. ,  Shah, Ajay K. ,  Wang, Shen H. ,  Semmelmeyer Mark W.

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

公开(公告)号：EP0271187A3

公开(公告)日：1990-04-11

申请号：EP87308811.6

申请日：1987-10-05

申请人： AMDAHL CORPORATION

发明人： Woffinden, Gary A. ,  Ertl, Robert A. ,  Thomas, Jeffrey A. ,  Robinson, Theodore S. ,  Millar, James P. ,  Finan, Christopher D. ,  Petolino, Joseph A., Jr. ,  Shah, Ajay K. ,  Wang, Shen H. ,  Semmelmeyer Mark W.

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

摘要： A computer system architecture implementing multiple central processing units, each including a split instruc­tion and operand cache, and that provides for the manage­ment of multiple copies (line pairs) of a memory line through the use of a line pair state is described. System­atic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture imple­ments the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the in­struction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depend­ing on whether the operand buffer destination is a memory line that is a member of a line pair.

公开(公告)号：EP0260862A3

公开(公告)日：1990-06-13

申请号：EP87307922.2

申请日：1987-09-08

申请人： AMDAHL CORPORATION

发明人： Thomas, Jeffrey A. ,  Robinson, Theodore S. ,  Ertl, Robert A. ,  Christense, Harold F. Jr.,

IPC分类号： G06F12/08

CPC分类号： G06F5/06 ,  G06F12/0804

摘要： A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit is described. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.