An image recording apparatus (10) is provided with relatively inexpensive circuitry for formatting image signals to a printhead (20). The circuitry includes an integrated circuit memory chip (52) having sufficient buffer memory sites for storing either a full line of image signals to be printed or image signals sufficient for filling more than one shift register assemblage (41) associated with the recording element driving means. Rasterized image signals are fed to said memory chip (52) in consecutive sequential order. A printhead (20) includes a plurality of recording elements (30) such as LED's arranged in a line configuration. Driving means (44) actuate said elements for recording on a line by line basis. Intermediate register means (57, 58) outputs the image signals in parallel to each of the shift register assemblages (41). Image signals are read from the memory chip (52) means to the intermediate register means (57, 58) in a non-consecutive sequential order. The control for writing data into and reading data from the memory chip comprises a counter (53) and several flip-flop registers which together provide addresses to locations in the memory chip (52).