发明公开
EP0328378A3 Dual-tracking phase-locked loop 失效
双跟踪相位锁定双向跟踪锁相环

Dual-tracking phase-locked loop
摘要:
A dual-tracking phase-locked loop circuit is provided for moving with minimum disruption from conventional PLL operation to processor-controlled tracking of another closely related clock. In addition to conventional PLL components the circuit comprises a processor-controlled up/down counter which may operate alternatively as a link in the loop or as providing the base-line frequency determining value at the time of transition from PLL to processor-controlled tracking operation, thereby ensuring none disruptive transition.
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