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    DEVICE AND METHOD FOR SIGNAL SYNTHESIS COMPENSATING THE OFFSET OF OPEN LOOP
    1.
    发明公开
    DEVICE AND METHOD FOR SIGNAL SYNTHESIS COMPENSATING THE OFFSET OF OPEN LOOP 审中-公开

    公开(公告)号：EP4459872A1

    公开(公告)日：2024-11-06

    申请号：EP23220430.5

    申请日：2023-12-28

    申请人： SKAIChips Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

    发明人： Jung, Yeon Jae ,  Kim, Dong Gyu ,  Lee, Kang Yoon

    IPC分类号： H03L7/14 ,  H03L7/093 ,  H03C3/09

    摘要： Disclosed is technology related to a signal synthesis apparatus that corrects an offset between a closed loop and an open loop to output a frequency-modulated signal. The signal synthesis apparatus includes a VCO configured to output a frequency signal in response to an input voltage, an energy storage unit configured to output a voltage using stored energy, a VCO input selector configured to connect the VCO to input of the energy storage unit in the case of a closed loop mode and connect the VCO to output of the energy storage unit in the case of an open loop mode, and a digital controller configured to control an operation mode of the VCO input selector and transmit an offset control signal for adjusting an offset of a voltage output from the energy storage unit to the energy storage unit.

    PHASE-LOCKED LOOP WITH DUAL INPUT REFERENCE AND DYNAMIC BANDWIDTH CONTROL
    5.
    发明公开
    PHASE-LOCKED LOOP WITH DUAL INPUT REFERENCE AND DYNAMIC BANDWIDTH CONTROL 审中-公开

    公开(公告)号：EP4016847A2

    公开(公告)日：2022-06-22

    申请号：EP21213371.4

    申请日：2021-12-09

    申请人： Synaptics, Incorporated

    发明人： POULSEN, Jens Kristian ,  CRESPI, Lorenzo

    IPC分类号： H03L7/087 ,  H03L7/197 ,  H03L7/14 ,  H03L7/107

    摘要： Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.

    A FRACTIONAL-N FREQUENCY SYNTHESIZER BASED ON A CHARGE-SHARING LOCKING TECHNIQUE
    6.
    发明公开
    A FRACTIONAL-N FREQUENCY SYNTHESIZER BASED ON A CHARGE-SHARING LOCKING TECHNIQUE 审中-公开

    公开(公告)号：EP3852272A1

    公开(公告)日：2021-07-21

    申请号：EP20151808.1

    申请日：2020-01-14

    申请人： University College Dublin, National University of Ireland, Dublin

    发明人： HU, Yizhe ,  SIRIBURANON, Teerachot ,  STASZEWSKI, Robert Bogdan

    IPC分类号： H03L7/099 ,  H03B5/12 ,  H03L7/14 ,  H03L7/10

    摘要： The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

    Clock synchronizer for aligning remote devices
    9.
    发明公开
    Clock synchronizer for aligning remote devices 审中-公开
    Taktsynchronisiereinrichtung zum Ausrichten von Fernvorrichtungen

    公开(公告)号：EP2843840A1

    公开(公告)日：2015-03-04

    申请号：EP14176889.5

    申请日：2014-07-14

    申请人： NXP B.V.

    发明人： Verlinden, Jos ,  van de Beek, Remco Cornelis Herman

    IPC分类号： H03L7/099 ,  H03L7/14 ,  H03L7/23

    摘要： Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

    摘要翻译： 本公开的各个方面涉及包括第一锁相环（PLL）电路和第二PLL电路的装置和方法。 第一PLL电路从非同步装置接收通过通信信道发送的载波信号，并产生PLL-PLL控制信号。 第二PLL电路接收稳定的基准振荡信号，响应于表示频率偏移的PLL-PLL控制信号，调整第二PLL电路的分数除数比。 第一PLL电路和第二PLL电路被配置为产生与载波信号同步的输出频率信号。

    Pll circuit
    10.
    发明公开
    Pll circuit 有权
    电路

    公开(公告)号：EP2782254A1

    公开(公告)日：2014-09-24

    申请号：EP14160829.9

    申请日：2014-03-20

    申请人： YAMAHA CORPORATION

    发明人： Sahara, Takuya

    IPC分类号： H03L7/14

    CPC分类号： H03L7/08 ,  H03L7/14

    摘要： A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector (101) for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device (107) for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.

    摘要翻译： 通过锁相环产生与外部时钟同步的产生时钟的PLL电路包括：第一检测器（101），用于检测产生的时钟是否与外部时钟同步;以及测量装置（107），用于测量 从外部时钟的上升到下降的高时间和从下降到上升的低时间中的至少一个。 在所生成的时钟和外部时钟同步的状态下，当检测到高电平时间或低电平时间的波动等于或大于预定值时，PLL电路固定所生成的时钟的频率 转换为在该时间点输出的频率，并继续输出具有固定频率的生成时钟。