发明公开
EP0328841A3 Asymmetrical delay generator for a clock chopper 失效
用于时钟切换器的不对称延迟发生器

Asymmetrical delay generator for a clock chopper
摘要:
An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
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