The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and