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公开(公告)号：EP0340870A3
公开(公告)日：1990-06-13
申请号：EP89201120.6
申请日：1989-05-01
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03L7/1978
摘要： The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and
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公开(公告)号：EP0340870A2
公开(公告)日：1989-11-08
申请号：EP89201120.6
申请日：1989-05-01
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03L7/1978
摘要： The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and
摘要翻译： 图1所示的数字调制器。 2在其输出端SO提供一个信号，其频率f1等于应用于其输入CLI的时钟频率f2的乘积，除法器DIV2除以的第二整数P和等于另一整数N之和的因子 分频器DIV3分频，有理数（F min + M）/ P。 由于后者小于单位，所以可以使用众所周知的累加器ACC和单周期去除电路CRC。 对于f2 = 3.25MHz，P = 16，N min = 17，可以获得以下调制的载波频率：其中M = @@@，其中m在0和519之间变化，并且
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